AREA EFFICIENT MEMORY CELL READ DISTURB MITIGATION
Granted: December 22, 2022
Application Number:
20220406371
A machine memory includes multiple memory cells. Word lines, each with at least one word line driver, are coupled to the memory cells along rows. The word line drivers of at least some adjacent pairs of the word lines are coupled together by a pull-down transistor, in a manner that reduces read disturb of the memory cells.
CMOS SIGNALING FRONT END FOR EXTRA SHORT REACH LINKS
Granted: November 3, 2022
Application Number:
20220353115
A transceiver circuit includes a receiver front end utilizing a ring oscillator, and a transmitter front end utilizing a pass-gate circuit in a first feedback path across a last-stage driver circuit. The transceiver circuit provides low impedance at low frequency and high impedance at high frequency, and desirable peaking behavior.
Clock Data Recovery Convergence In Modulated Partial Response Systems
Granted: September 29, 2022
Application Number:
20220311592
A clock data recovery circuit detects illegal decisions for received data, accumulates a phase gradient for the data, determines a number of the illegal decisions in a configured window for receiving the data, and if the number of the illegal decisions exceeds a pre-defined number in the window, applies a sum of the accumulated phase gradient and a phase increment having a sign of the accumulated phase gradient to a clock circuit for the data receiver.
METHOD FOR ASSESSING THE QUALITY OF A ROBOTIC GRASP ON 3D DEFORMABLE OBJECTS
Granted: September 22, 2022
Application Number:
20220297297
Candidate grasping models of a deformable object are applied to generate a simulation of a response of the deformable object to the grasping model. From the simulation, grasp performance metrics for stress, deformation controllability, and instability of the response to the grasping model are obtained, and the grasp performance metrics are correlated with robotic grasp features.
Reinforcement driven standard cell placement
Granted: September 15, 2022
Application Number:
20220292335
An automatic standard cell layout generator that generates circuit layouts for an industry standard cell library on an advanced technology node leverages reinforcement learning (RL) to generate device placements in the layouts and also to fix design rule violations during routing. A genetic algorithm is utilized to generate routing candidates to which a reinforcement learning model is applied to correct the design rule constraint violations incrementally. A design rule checker provides…
Phase Locked Loop with Low Reference Spur
Granted: September 8, 2022
Application Number:
20220286138
A calibration circuit including multiple charge pumps supplying a voltage controlled oscillator along different paths, one path being an integration path from a first one of the charge pumps to the voltage controlled oscillator, and one path being a proportional path from a second one of the charge pumps to the voltage controlled oscillator. A phase locked loop of the calibration circuit utilizes a switch capacitor circuit to reduce reference spur and improve the accuracy of clock edges…
TECHNIQUES TO IMPROVE CURRENT REGULATOR CAPABILITY TO PROTECT THE SECURED CIRCUIT FROM POWER SIDE CHANNEL ATTACK
Granted: May 12, 2022
Application Number:
20220149728
This disclosure relates to current flattening circuits for an electrical load. The current flattening circuits incorporate randomize various parameters to add noise onto the supply current. This added noise may act to reduce the signal to noise ratio in the supply current, increasing the difficulty of identifying a computational artifact signal from power rail noise.
SCALABLE LIGHT-WEIGHT PROTOCOLS FOR WIRE-SPEED PACKET ORDERING
Granted: March 24, 2022
Application Number:
20220095017
A communication method between a source device and a target device utilizes speculative connection setup between the source device and the target device, target-device-side packet ordering, and fine-grained ordering to remove packet dependencies.
Efficient Neural Network Accelerator Dataflows
Granted: March 10, 2022
Application Number:
20220076110
A distributed deep neural net (DNN) utilizing a distributed, tile-based architecture includes multiple chips, each with a central processing element, a global memory buffer, and a plurality of additional processing elements. Each additional processing element includes a weight buffer, an activation buffer, and vector multiply-accumulate units to combine, in parallel, the weight values and the activation values using stationary data flows.
EFFICIENT SOFTMAX COMPUTATION
Granted: March 3, 2022
Application Number:
20220067513
Solutions improving efficiency of Softmax computation applied for efficient deep learning inference in transformers and other neural networks. The solutions utilize a reduced-precision implementation of various operations in Softmax, replacing ex with 2x to reduce instruction overhead associated with computing ex, and replacing floating point max computation with integer max computation. Further described is a scalable implementation that decomposes Softmax into UnNormalized Softmax and…
STANDARD CELL LAYOUT GENERATION WITH APPLIED ARTIFICIAL INTELLIGENCE
Granted: January 27, 2022
Application Number:
20220027546
A genetic algorithm is utilized to generate routing candidates to which a reinforcement learning model is applied to correct the design rule constraint violations incrementally. A design rule checker provides feedback on the violations to the reinforcement learning model and the model learns how to fix the violations. A layout device placer based upon a simulated annealing method may also be utilized.
TECHNIQUES FOR DIVERGENT THREAD GROUP EXECUTION SCHEDULING
Granted: January 27, 2022
Application Number:
20220027194
Warp sharding techniques to switch execution between divergent shards on instructions that trigger a long stall, thereby interleaving execution between diverged threads within a warp instead of across warps. The technique may be applied to mitigate pipeline stalls in applications with low warp occupancy and high divergence. Warp data cache locality may also be improved by concentrating memory accesses within a warp rather than spreading them across warps.
FOVEATION AND SPATIAL HASHING IN LAYER-BASED COMPUTER-GENERATED HOLOGRAMS
Granted: January 27, 2022
Application Number:
20220026715
The computational scaling challenges of holographic displays are mitigated by techniques for generating holograms that introduce foveation into a wave front recording planes approach to hologram generation. Spatial hashing is applied to organize the points or polygons of a display object into keys and values.
ADVERSARIAL SCENARIOS FOR SAFETY TESTING OF AUTONOMOUS VEHICLES
Granted: December 16, 2021
Application Number:
20210389769
Techniques to generate driving scenarios for autonomous vehicles characterize a path in a driving scenario according to metrics such as narrowness and effort. Nodes of the path are assigned a time for action to avoid collision from the node. The generated scenarios may be simulated in a computer.
TENSOR-BASED DRIVING SCENARIO CHARACTERIZATION
Granted: December 16, 2021
Application Number:
20210387643
Techniques to characterize driving scenarios for autonomous vehicles characterize a path in a driving scenario according to metrics such as narrowness and effort. The scenarios may be characterized using a tree-based or tensor-based approach.
Adaptive Pixel Sampling Order for Temporally Dense Rendering
Granted: November 4, 2021
Application Number:
20210344944
A method dynamically selects one of a first sampling order and a second sampling order for a ray trace of pixels in a tile where the selection is based on a motion vector for the tile. The sampling order may be a bowtie pattern or an hourglass pattern.
USE OF STASHING BUFFERS TO IMPROVE THE EFFICIENCY OF CROSSBAR SWITCHES
Granted: November 4, 2021
Application Number:
20210344616
A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.
FOVEATED DISPLAY FOR AUGMENTED REALITY
Granted: November 4, 2021
Application Number:
20210341741
An augmented reality display system includes a first beam path for a foveal inset image on a holographic optical element, a second beam path for a peripheral display image on the holographic optical element, and pupil position tracking logic that generates control signals to set a position of the foveal inset as perceived through the holographic optical element, to determine the peripheral display image, and to control a moveable stage.
CURRENT FLATTENING CIRCUIT FOR PROTECTION AGAINST POWER SIDE CHANNEL ATTACKS
Granted: October 28, 2021
Application Number:
20210334411
Various implementations of a current flattening circuit are disclosed, including those utilizing a feedback current regulator, a feedforward current regulator, and a constant current source.
TECHNIQUES TO IMPROVE CURRENT REGULATOR CAPABILITY TO PROTECT THE SECURED CIRCUIT FROM POWER SIDE CHANNEL ATTACK
Granted: October 28, 2021
Application Number:
20210336536
This disclosure relates to current flattening circuits for an electrical load. The current flattening circuits incorporate randomize various parameters to add noise onto the supply current. This added noise may act to reduce the signal to noise ratio in the supply current, increasing the difficulty of identifying a computational artifact signal from power rail noise.
