TENSOR-BASED DRIVING SCENARIO CHARACTERIZATION
Granted: December 16, 2021
Application Number:
20210387643
Techniques to characterize driving scenarios for autonomous vehicles characterize a path in a driving scenario according to metrics such as narrowness and effort. The scenarios may be characterized using a tree-based or tensor-based approach.
Adaptive Pixel Sampling Order for Temporally Dense Rendering
Granted: November 4, 2021
Application Number:
20210344944
A method dynamically selects one of a first sampling order and a second sampling order for a ray trace of pixels in a tile where the selection is based on a motion vector for the tile. The sampling order may be a bowtie pattern or an hourglass pattern.
USE OF STASHING BUFFERS TO IMPROVE THE EFFICIENCY OF CROSSBAR SWITCHES
Granted: November 4, 2021
Application Number:
20210344616
A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.
FOVEATED DISPLAY FOR AUGMENTED REALITY
Granted: November 4, 2021
Application Number:
20210341741
An augmented reality display system includes a first beam path for a foveal inset image on a holographic optical element, a second beam path for a peripheral display image on the holographic optical element, and pupil position tracking logic that generates control signals to set a position of the foveal inset as perceived through the holographic optical element, to determine the peripheral display image, and to control a moveable stage.
TECHNIQUES TO IMPROVE CURRENT REGULATOR CAPABILITY TO PROTECT THE SECURED CIRCUIT FROM POWER SIDE CHANNEL ATTACK
Granted: October 28, 2021
Application Number:
20210336536
This disclosure relates to current flattening circuits for an electrical load. The current flattening circuits incorporate randomize various parameters to add noise onto the supply current. This added noise may act to reduce the signal to noise ratio in the supply current, increasing the difficulty of identifying a computational artifact signal from power rail noise.
CURRENT FLATTENING CIRCUIT FOR PROTECTION AGAINST POWER SIDE CHANNEL ATTACKS
Granted: October 28, 2021
Application Number:
20210334411
Various implementations of a current flattening circuit are disclosed, including those utilizing a feedback current regulator, a feedforward current regulator, and a constant current source.
DEEP LEARNING BASED IDENTIFICATION OF DIFFICULT TO TEST NODES
Granted: September 23, 2021
Application Number:
20210295169
Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.
Circuit Solution for Managing Power Sequencing
Granted: September 23, 2021
Application Number:
20210294410
A circuit includes a supply power detector in a first power domain and a ratioed inverter in the first power domain or a second, different power domain. The supply power detector includes an output coupled to an input of the ratioed inverter, and an output of the ratioed inverter provides a power sequencing signal for the second power domain.
FAST TRIGGERING ELECTROSTATIC DISCHARGE PROTECTION
Granted: September 9, 2021
Application Number:
20210281067
An electrostatic discharge protection circuit is disclosed. It comprises a stacked drain-ballasted NMOS devices structure and a gate bias circuit. The gate bias circuit includes an inverter, a first gate bias output terminal, and a second gate bias output terminal. The first gate bias output terminal is coupled to a gate of a first one of the drain-ballasted NMOS devices. The second gate bias output terminal runs from an output of the inverter to a gate of a second one of the…
ADDRESSING CACHE SLICES IN A LAST LEVEL CACHE
Granted: August 19, 2021
Application Number:
20210255963
“A system in having M memory controllers between a first memory and a second memory having N operative memory slices, where N and M are not evenly divisible, includes logic to operate the M memory controllers to linearly distribute addresses of the second memory across the N operative memory slices. The system may be utilized in commercial applications such as data centers, autonomous vehicles, and machine learning.”
AVERAGE POWER ESTIMATION USING GRAPH NEURAL NETWORKS
Granted: May 27, 2021
Application Number:
20210158155
A graph neural network for average power estimation of netlists is trained with register toggle rates over a power window from an RTL simulation and gate level netlists as input features. Combinational gate toggle rates are applied as labels. The trained graph neural network is then applied to infer combinational gate toggle rates over a different power window of interest and/or different netlist.
LAYOUT PARASITICS AND DEVICE PARAMETER PREDICTION USING GRAPH NEURAL NETWORKS
Granted: May 27, 2021
Application Number:
20210158127
A graph neural network to predict net parasitics and device parameters by transforming circuit schematics into heterogeneous graphs and performing predictions on the graphs. The system may achieve an improved prediction rate and reduce simulation errors.
Data Recovery Technique for Time Interleaved Receiver in Presence of Transmitter Pulse Width Distortion
Granted: May 13, 2021
Application Number:
20210143824
This disclosure relates to a receiver comprising a clock and data recovery loop and a phase offset loop. The clock and data recovery loop may be controlled by a sum of gradients for a plurality of data interleaves. The phase offset loop may be controlled by an accumulated differential gradient for each of the data interleaves.
FULL ADDER CELL WITH IMPROVED POWER EFFICIENCY
Granted: April 29, 2021
Application Number:
20210124559
This disclosure relates to an adder circuit. The adder circuit comprises an operand input and a second operand input to an XNOR cell. The XNOR cell may be configured to provide the operand input and the second operand input to both a NAND gate and a first OAI cell. A second OAI cell may transform the output of the XNOR cell into a carry out signal.
FULL ADDER CELL WITH IMPROVED POWER EFFICIENCY
Granted: April 29, 2021
Application Number:
20210124558
An adder circuit provides a first operand input and a second operand input to an XNOR cell. The XNOR cell transforms these inputs to a propagate signal that is applied to an OAT cell to produce a carry out signal. A third OAT cell transforms a third operand input and the propagate signal into a sum output signal.
ADDRESSING CACHE SLICES IN A LAST LEVEL CACHE
Granted: March 25, 2021
Application Number:
20210089465
An addressing scheme in systems utilizing a number of operative memory slices in a last level cache that is not evenly divisible by a number of memory channels utilizes the operative slices exposes the full last level cache bandwidth and capacity to data processing logic in a high-performance graphics system.
DRIVER GAZE TRACKING SYSTEM FOR USE IN VEHICLES
Granted: March 25, 2021
Application Number:
20210088784
A gaze tracking system for use by the driver of a vehicle includes an opaque frame circumferentially enclosing a transparent field of view of the driver, light emitting diodes coupled to the opaque frame for emitting infrared light onto various regions of the driver's eye gazing through the transparent field of view, and diodes for sensing intensity of infrared light reflected off of various regions of the driver's eye.
Reference Noise Compensation for Single-Ended Signaling
Granted: March 18, 2021
Application Number:
20210083837
A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction is computed as a global offset value based on a clock duty…
REFERENCE NOISE COMPENSATION FOR SINGLE-ENDED SIGNALING
Granted: March 18, 2021
Application Number:
20210083836
A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction based on a clock duty cycle error is applied to data…
PACKAGE LEVEL POWER GATING
Granted: February 11, 2021
Application Number:
20210043574
A die package is disclosed through which power domains within the chip may be isolated by removing vias within the package substrate, rather than power gating. Multiple substrate options may be configured without specific vias. This eliminates the need to design power gating circuitry into the die, freeing up that die area for more functional logic. The solution allows the die package to retain the same pinout for use by PCB designers, regardless of which power domains are gated.
