Systems and methods for decoding data for solid-state memory
Granted: July 14, 2015
Patent Number:
9081701
Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be reliably implemented using various types of memory cells, including relatively inexpensive multi-level cell flash. One embodiment intelligently coordinates remapping of bad blocks with error correction code control, which eliminates the tables used to avoid bad blocks.
Gain calibration for a timing error detector
Granted: June 30, 2015
Patent Number:
9071320
Apparatus and methods calibrate and control detector gain in a Mueller-Muller timing detector. A Mueller-Muller circuit obtains timing information for a received signal in which the receiving device samples the signal once per baud period.
Transmitter data path single-ended duty cycle correction for EMI reduction
Granted: June 30, 2015
Patent Number:
9071293
The present disclosure provides a means to adjust the relative location of output rising and falling transitions to reduce single-ended duty cycle distortion (DCD) effects in the output data stream originating from the transmitter data path. This serves to improve high-speed single-ended signal characteristics and reduce electromagnetic interference (EMI). Another feature enabled by embodiments of the present disclosure is polarity skew (also referred to as differential skew) reduction…
Electro-mechanical oscillator and method for generating a signal
Granted: June 30, 2015
Patent Number:
9071194
An oscillator and method for generating a signal are provided. The oscillator comprises an electro-mechanical resonator and a reconfigurable oscillator driver. The reconfigurable oscillator driver starts the oscillator in single-ended mode to avoid latching and transitions the oscillator to differential mode in such a manner as to sustain oscillations therein. The reconfigurable oscillator driver comprises two back-to-back banks of inverters and an adjustable feedback resistor. In…
Systems and methods for storing data for solid-state memory
Granted: June 9, 2015
Patent Number:
9053012
Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be reliably implemented using various types of memory cells, including relatively inexpensive multi-level cell flash. One embodiment intelligently coordinates remapping of bad blocks with error correction code control, which eliminates the tables used to avoid bad blocks.
System and method for tolerating a failed page in a flash device
Granted: June 2, 2015
Patent Number:
9047214
Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application. A page is associated with a set of primary ECC codewords, and a page stripe is associated with a set of secondary codewords and primary over secondary parity (PoSP) ECC codewords. Two or…
Systems and methods for adapting to changing characteristics of multi-level cells in solid-state memory
Granted: May 5, 2015
Patent Number:
9026867
Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be reliably implemented using various types of memory cells, including relatively inexpensive multi-level cell flash. One embodiment intelligently coordinates remapping of bad blocks with error correction code control, which eliminates the tables used to avoid bad blocks.
Multiplexing low-order to high-order ODU signals in an optical transport network
Granted: May 5, 2015
Patent Number:
9025594
A method and apparatus are provided for multiplexing one or more Low-Order (LO) ODUj/ODUflex clients into a High-Order (HO) ODUk in an Optical Transport Network (OTN). LO bytes are multiplexed in accordance with a tributary slot assignment for a selected LO ODUj of the HO ODUk stream using a permutation matrix. In an implementation, each byte on each ingress port of a W-port space-time-space switch is configurably assigned to an associated timeslot of an associated egress port, using…
Systems and methods for adaptively selecting among different error correction coding schemes in a flash drive
Granted: April 28, 2015
Patent Number:
9021337
Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application.
System and method for automated test script generation
Granted: April 28, 2015
Patent Number:
9021440
A system and method for automatically generating a test script includes receiving a test case flow that includes steps, nodes, and sub-nodes, wherein each sub-node is associated with a use-case based application programming interface (UC-API), for each sub-node of the test case flow retrieving a template array corresponding to the UC-API associated with the sub-node, generating a test array wherein for each node in a step, generating a node array wherein the elements of each node array…
Systems and methods for redundantly storing error correction codes in a flash drive with secondary parity information spread out across each page of a group of pages
Granted: April 28, 2015
Patent Number:
9021336
Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application. Both primary parity symbols for primary codewords and secondary parity symbols for secondary codewords are generated. The secondary parity symbols are spread out across each page of a…
Systems and methods for recovering data from failed portions of a flash drive
Granted: April 28, 2015
Patent Number:
9021333
Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application.
Power saving for FIFO buffer without performance degradation
Granted: April 28, 2015
Patent Number:
9021280
A power-saving method for a first-in-first-out (FIFO) buffer implemented in a memory. The memory is segmented into a plurality of logical segments. For each logical segment, for each power saving mode, a recovery time and recovery overhead to an operational mode, and a transition overhead for transitioning the logical segment into the power saving mode, are determined. During each clock cycle, a determination is made as to whether a net power saving will result by entering each logical…
Search table for data networking matching
Granted: April 28, 2015
Patent Number:
9020953
A high efficiency search table is implemented with a multiple hash algorithm. The search table allows for exact match searching of arbitrary data sets with fixed latency. The probability of collisions from the hash algorithms is reduced through the use of oversized pointer tables allowing for a level of indirection between hash values and table entries. In the event of a collision in all hash functions, a firmware assisted cuckoo algorithm is employed to resolve the collision.
Method and apparatus for sampling point optimization
Granted: April 28, 2015
Patent Number:
9020085
A method and apparatus for timing optimization are disclosed, which rely on information gathered from a timing detection circuit to find the optimal sampling point of a data recovery system. In an implementation, a timing shift is optimized based on Gardner detector data. In an example, a Gardner detector, or an early and late extraction portion thereof, is added to the data path, and the data path clock is shifted so that it is centered on the data transition mean. In an implementation,…
Analog finite impulse response adaptation method and apparatus
Granted: April 28, 2015
Patent Number:
9020022
A SerDes receiver comprising: an input for receiving a signal, the signal having a baud rate; an Analog Finite Impulse Response equalizer (AFIR) for equalizing the received signal, the AFIR comprising: a pre-cursor tap having a pre-cursor coefficient; a cursor tap having a cursor coefficient, the cursor coefficient being constrained to a non-negative value; and a post-cursor tap having a post-cursor coefficient; an adaptation block coupled to the AFIR, the adaptation block configured to…
Enabling RX signal path synchronization and alignment signals in a highly integrated TX RFIC
Granted: April 28, 2015
Patent Number:
9020011
A transmit (TX) signal path circuit in a multiple-input, multiple-output (MIMO) transceiver responsive to a digital front end (DFE) for generating receive (RX) path phase alignment signals is disclosed. A digital up-conversion block uses a first numerically-controlled oscillator (NCO) for generating digital intermediate frequency (IF) signals for ordinary TX signal generation, and a different, second NCO for generating digital IF signals for RX phase alignment signal generation. An RF…
Method and system for transporting constant bit rate clients across a packet interface
Granted: April 28, 2015
Patent Number:
9019997
This disclosure describes a method and apparatus for signaling the phase and frequency of OTN and Constant Bit Rate (CBR) clients in an OTN network. The principles discussed are applicable when multiple stages of OTN multiplexing and demultiplexing are utilized. They are also applicable for use with the Generic Mapping Procedure (GMP) and Asynchronous Mapping Procedure (AMP). A method to use the phase and frequency of an ODUk/ODUflex to adjust a local reference clock to enable the…
Distributed electrostatic discharge protection circuit
Granted: April 28, 2015
Patent Number:
9019669
A distributed electrostatic discharge (ESD) protection circuit is provided. At frequencies beyond 10 GHz, the parasitic capacitance of primary ESD protection voltage clamping devices, such as diodes, hampers adequate insertion and return loss, in spite of lumped inductor tuning. An ESD protection circuit according to an embodiment of the present disclosure solves the problem by distributing the diode, or voltage clamping device, capacitance among several sections of an artificial…
Post-distortion filter for reducing sensitivity to receiver nonlinearities
Granted: April 14, 2015
Patent Number:
9008228
Methods and apparatus for reducing sensitivity to nonlinearities in the receiver of a digital communications system are disclosed. One aspect can be referred to as a Post-Distortion Decision Feedback Equalizer (PDFE). A gain stage is often implemented as a variable gain amplifier (VGA), and can introduce significant nonlinearities, a problem exacerbated by signals with a large peak-to-average ratio (PAR). One embodiment provides feed forward information from the VGA regarding its status…
