Synopsys Patent Applications

Pre-Silicon Design Rule Evaluation

Granted: February 9, 2017
Application Number: 20170039308
Roughly described, a method for developing a set of design rules for a fabrication process in development includes, for each of several candidate DRUTs for the fabrication process, laying our a logic cell based on the DRUT, the logic cell having at least one transistor and at least one interconnect, simulating fabrication of the logic cell according to the fabrication process and the layout, simulating behavior of the logic cell structure, including characterizing the combined behavior…

2D MATERIAL SUPER CAPACITORS

Granted: February 9, 2017
Application Number: 20170040411
Devices and methods are described relating to capacitor energy storage devices that are small in size and have a high energy stored to volume ratio. The capacitor devices include 2D material electrodes. The capacitor devices offer very fine granularity with high stacking possibilities which may be used in super capacitors and capacitor arrays. The devices include interleaved laminations 2D material electrode layers, for example graphene, and dielectric layers, for example Hafnium Oxide.…

Identifying Software Components in a Software Codebase

Granted: February 2, 2017
Application Number: 20170032117
Systems, methods, and computer program embodiments are disclosed for detecting software components in a software codebase. In an embodiment, a source file containing source code may be received, and a code signature may be generated for the source file based on a determined structure of the source code. The generated code signature may then be compared to signatures stored in a reference database to identify matching software files. In an embodiment, the reference database may store a…

Methods for Manufacturing Integrated Circuit Devices Having Features With Reduced Edge Curvature

Granted: January 26, 2017
Application Number: 20170025496
A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in etching the line. Techniques are described for processing a line of crystalline phase material which has already been etched using the mask element, in a manner which straightens an etched sidewall surface of the line. The straightened sidewall…

POWER-AND-GROUND (PG) NETWORK CHARACTERIZATION AND DISTRIBUTED PG NETWORK CREATION FOR HIERARCHICAL CIRCUIT DESIGNS

Granted: January 19, 2017
Application Number: 20170017746
A chip layout can include a top-level portion and a set of blocks. The power-and-ground (PG) network for the chip layout can be specified by a set of chip-level PG constraints that is defined using a PG constraint definition language. The set of chip-level PG constraints can be characterized into new sets of PG constraints that correspond to smaller regions of the chip layout, e.g., a set of top-level PG constraints that corresponds to the top-level portion, and a set of block-level PG…

SYSTEM AND METHOD FOR HIERARCHICAL POWER VERIFICATION

Granted: January 12, 2017
Application Number: 20170011138
A hierarchical power verification system and method creates abstract models of power behavior of modules that it successfully verifies. The abstract models simplify the module definition by omitting internal module details but provide sufficient information for power verification of higher level modules that incorporate this abstracted module. Design blocks are replaced with these abstract power models, resulting in reduced run-time and memory requirements. The power models can include…

METHOD AND APPARATUS FOR WORD-LEVEL NETLIST PREPROCESSING AND ANALYSIS USING SAME

Granted: January 12, 2017
Application Number: 20170011140
A computer implemented representation of a circuit design is reduced by representing the circuit design as a data structure defining a netlist. A first set of nodes is identified in the netlist that includes datapath nodes, preferably nodes that do not intermingle data and control. The first set of nodes is segmented into segment widths that correspond to uniformly treated segments of the corresponding words. A second set of nodes, including nodes that intermingle data and control, are…

NETLIST ABSTRACTION FOR CIRCUIT DESIGN FLOORPLANNING

Granted: January 5, 2017
Application Number: 20170004240
Systems and methods are described for creating a netlist abstraction that provides full-chip context for performing circuit design floorplanning. The netlist abstraction can include a top-level netlist abstraction that corresponds to the top-level portion of the netlist, and a physical block netlist abstraction for each physical block in the circuit design. Each physical block netlist abstraction can retain macros that are in the physical block.

LOOK-AHEAD TIMING PREDICTION FOR MULTI-INSTANCE MODULE (MIM) ENGINEERING CHANGE ORDER (ECO)

Granted: January 5, 2017
Application Number: 20170004244
Some embodiments determine a merged timing graph for a multi-instance module (MIM), wherein each node in the merged timing graph corresponds to a pin in the MIM, and wherein each node in the merged timing graph stores timing information associated with the corresponding pins in multiple instances of the MIM in a circuit design. The embodiments can then determine an ECO for the MIM based on the merged timing graph.

METHOD AND SYSTEM FOR CHECKING AND CORRECTING SHOOT-THROUGH IN RTL SIMULATION

Granted: November 24, 2016
Application Number: 20160342727
In a method of checking an integrated circuit design prior to running a simulation, a shoot-through RTL Checker reads RTL design files, uses a simulator delta cycle definitions to compute clock delta delays, and helps to correct and report any conditions that are expected will cause the simulation to generate incorrect results, in particular shoot-through conditions at circuit memory elements such as source and destination flip-flops or registers.

METHOD AND APPARATUS FOR AUTOMATIC RELATIVE PLACEMENT GENERATION FOR CLOCK TREES

Granted: November 17, 2016
Application Number: 20160335376
Methods and apparatuses are disclosed for automatic relative placement of part of a clock tree in the course of generating a placed, routed, and optimized circuit design.

MULTI-SCALE SIMULATION INCLUDING FIRST PRINCIPLES BAND STRUCTURE EXTRACTION

Granted: November 17, 2016
Application Number: 20160335381
Electronic design automation modules include a first tool and a second tool. The first tool includes ab initio simulation procedures configured to use input parameters to produce information about a band structure of a simulated material on a first simulation scale specified at least in part by the input parameters. The second tool includes a simulation procedure configured to used information about the band structure of the simulated material produced by the first tool to extract…

3D RESIST PROFILE AWARE ETCH-BIAS MODEL

Granted: November 17, 2016
Application Number: 20160335384
Systems and techniques for using a three-dimension (3D) resist profile aware etch-bias model are described. A 3D resist profile aware etch-bias model can be calibrated based on empirical data. Next, the 3D resist profile aware etch-bias model can be used in one or more applications, including, but not limited to, lithography verification, etch correction, optical proximity correction, and assist feature placement.

Design Tools For Converting a FinFet Circuit into a Circuit Including Nanowires and 2D Material Strips

Granted: November 17, 2016
Application Number: 20160335387
An integrated circuit design tool includes a cell library. An entry in the cell library comprises a specification of the cell including a first transistor and a second transistor. The first transistor can include a first set of nanowires or 2D material strips arranged in parallel to form a channel structure, and a gate conductor disposed across the first set of nanowires or 2D material strips. The second transistor can include a second set of nanowires or 2D material strips arranged in…

CELLS HAVING TRANSISTORS AND INTERCONNECTS INCLUDING NANOWIRES OR 2D MATERIAL STRIPS

Granted: November 10, 2016
Application Number: 20160329313
An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a plurality of transistors and an interconnect; wherein a transistor in the plurality has a channel comprising one or more nanowires or 2D material…

SYSTEM AND METHOD FOR REACTIVE INITIALIZATION BASED FORMAL VERIFICATION OF ELECTRONIC LOGIC DESIGN

Granted: October 13, 2016
Application Number: 20160300009
A system and method use reactive initialization to facilitate formal verification of an electronic logic design. The system verifies that a part of the logic design correctly transitions through a sequence of states by automatically assigning an initial state value. The system interacts with a correction-unit to provide meaningful feedback of verification failures, making it possible for the correction-unit to correct the failures or add new constraints that allow the verification to…

CLOCK-DOMAIN-CROSSING SPECIFIC DESIGN MUTATIONS TO MODEL SILICON BEHAVIOR AND MEASURE VERIFICATION ROBUSTNESS

Granted: October 6, 2016
Application Number: 20160292331
Methods and apparatuses related to clock-domain-crossing (CDC) specific design mutations to model silicon behavior and measure verification robustness are described. CDC signal paths can be identified in a circuit design. Next, synchronization circuitry associated with the CDC signal paths can be identified. Design mutations can be added to the identified synchronization circuitry. The design mutations can then be used during functional verification to measure verification robustness of…

SYSTEM AND METHOD FOR POWER VERIFICATION USING EFFICIENT MERGING OF POWER STATE TABLES

Granted: October 6, 2016
Application Number: 20160292346
A power verification system requires a combination of design and its power intent. A power intent (PI) input specifies the power architecture of a design through specification of power/voltage domains, their corresponding power supplies and a collection of power management devices. Power state tables (PSTs) specified in PI capture the legal combinations of power states (voltage values) for the various sets of supply nets or supply ports of a design. A power verification system requires…

SCALABLE CHIP PLACEMENT

Granted: September 29, 2016
Application Number: 20160283632
Some embodiments can receive a netlist for the circuit design, wherein the netlist is divided into a set of blocks and a top-level netlist. Next, the embodiments can create (1) a top-level netlist abstraction based on the top-level netlist, and (2) for each block in the set of blocks, create a block abstraction based on a portion of the netlist that is in the block and create virtual pin cells in the block, wherein each virtual pin cell corresponds to a connection that crosses a boundary…

NANOWIRE OR 2D MATERIAL STRIPS INTERCONNECTS IN AN INTEGRATED CIRCUIT CELL

Granted: September 29, 2016
Application Number: 20160284704
An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a circuit including a first transistor, a second transistor, and an interconnect connecting a terminal of the first transistor to a terminal of the…