GENERATING SIMULATION-FRIENDLY COMPACT PHYSICAL MODELS FOR PASSIVE STRUCTURES
Granted: September 9, 2021
Application Number:
20210279395
A system and method for generating simulation-friendly compact physical models for passive structures is disclosed. The method includes generating an impedance map specifying impedances at a plurality of frequencies corresponding to one or more port-pairs of a circuit component using a processor to extract a plurality of impedance values between the one or more port-pairs based on a first value for each parameter of a plurality of parameters of the circuit component. The method includes…
AUTOMATIC TEST PATTERN GENERATION (ATPG) FOR PARAMETRIC FAULTS
Granted: August 26, 2021
Application Number:
20210264087
Systems and methods for automatic test pattern generation (ATPG) for parametric faults are described. A model may be constructed to predict a measurement margin for an integrated circuit (IC) design based on a random sample of random variables. A set of failure events may be determined for the IC design using the model, where each failure event may correspond to a set of values of the random variables that is expected to cause a metric for the IC design to violate a threshold.
INCLUSION OF STOCHASTIC BEHAVIOR IN SOURCE MASK OPTIMIZATION
Granted: August 26, 2021
Application Number:
20210263405
A method of generating a mask used in fabrication of a semiconductor device includes, in part, selecting a source candidate, generating a process simulation model that includes a stochastic variance band model in response to the selected source candidate, performing a first optical proximity correction (OPC) on the data associated with the mask in response to the process simulation model, assessing one or more lithographic evaluation metrics in response to the OPC mask data, computing a…
Debugging non-detected faults using sequential equivalence checking
Granted: July 15, 2021
Application Number:
20210216694
Techniques and systems for classifying non-detected faults (NDFs) in a formal verification test-bench are described. A sequential equivalence checking formulation can be constructed based on an integrated circuit (IC) design and a set of NDFs, wherein the set of NDFs do not falsify a first set of properties of the IC design, wherein said constructing the sequential equivalence checking formulation comprises creating a second set of properties based on the set of NDFs, wherein each…
Correlation between Emission Spots Utilizing CAD Data in Combination with Emission Microscope Images
Granted: July 1, 2021
Application Number:
20210199714
A method includes capturing a photon emission microscope (PEM) image of an integrated circuit (IC), and identifying emission sites in the PEM image, where the emission sites are associated with a leakage current. A set of common nets is found that connects multiple emission sites using layout data and/or netlist data in computer-aided design (CAD) data. From the layout data and/or netlist data, a critical net is identified from the set of common nets connecting a threshold number of…
Temperature Tracked Dynamic Keeper Implementation to Enable Read Operations
Granted: June 24, 2021
Application Number:
20210193219
A static random access memory (SRAM) system includes a plurality of SRAM storage cells, each of the plurality of SRAM storage cells coupled to a respective read bit line, and a dynamic keeper coupled to the read bit line. The dynamic keeper includes a first keeper to support a read operation at a first temperature range, and a second keeper to support the read operation at a second temperature range, and a temperature-sensitive control circuit to select the first keeper or the second…
NET-BASED WAFER INSPECTION
Granted: June 24, 2021
Application Number:
20210192116
A defect map may be created by merging defects at locations on multiple dies that include copies of an integrated circuit (IC). Layout shapes or nets may be determined that overlap with the defects in the defect map. Next, connectivity between the layout shapes or nets may be determined. The defects may then be grouped into defect groups based on the connectivity between the layout shapes or nets, where each defect group comprises defects that overlap with layout shapes or nets that are…
PREDICTING DEFECT RATE BASED ON LITHOGRAPHIC MODEL PARAMETERS
Granted: April 22, 2021
Application Number:
20210116817
A calibrated lithographic model may be used to generate a lithographic model output based on an integrated circuit (IC) design layout. Next, at least a chemical parameter may be extracted from the lithographic model output. A calibrated defect rate model may then be used to predict a defect rate for the IC design layout based on the chemical parameter.
ENHANCED READ SENSING MARGIN FOR SRAM CELL ARRAYS
Granted: March 25, 2021
Application Number:
20210090639
This disclosure describes a memory cell array with enhanced read sensing margin. The memory cell array includes a write port and a read port being connected through first and second data storage lines. The memory cell array further includes multiple word lines and bit lines arranged in rows and columns such that the read port is coupled to a read word line, a read bit line, and a virtual ground. The read port includes a first transistor coupled to at least the read bit line and the…
MACHINE-LEARNING DRIVEN PREDICTION IN INTEGRATED CIRCUIT DESIGN
Granted: March 11, 2021
Application Number:
20210073456
Training data is collected for each training integrated circuit (IC) design of a set of training IC designs by: extracting a first set of IC design features in a first stage of an IC design flow, and extracting a first set of IC design labels in a second stage of the IC design flow, where the first stage of the IC design flow occurs earlier than the second stage of the IC design flow in the IC design flow. Next, a machine learning model is trained based on the training data.
APPLYING RETICLE ENHANCEMENT TECHNIQUE RECIPES BASED ON FAILURE MODES PREDICTED BY AN ARTIFICIAL NEURAL NETWORK
Granted: February 18, 2021
Application Number:
20210048741
Training data may be collected for each design intent in a set of design intents by identifying a set of failures that is expected to occur when the design intent is manufactured, and recording a failure mode and a location of each failure in the set of failures. Next, the training data may be used to train a machine learning model, e.g., an artificial neural network, to predict failure modes and locations of failures. The trained machine learning model, e.g., trained artificial neural…
REGISTER TRANSFER LEVEL (RTL) IMAGE RECOGNITION
Granted: January 21, 2021
Application Number:
20210019461
A method of generating images from Register Transfer Level (RTL) code for clone detection or code verification is provided. The method includes obtaining a first RTL code, extracting first RTL constructs from the first RTL code, generating a first array from the extracted first RTL constructs, generating a first RTL image representation (RIR) image from the generated first array, wherein color in the first RIR image corresponds to values included in the first array, comparing the…
CRYSTAL ORIENTATION ENGINEERING TO ACHIEVE CONSISTENT NANOWIRE SHAPES
Granted: November 26, 2020
Application Number:
20200373388
The independent claims of this patent signify a concise description of embodiments. Disclosed is technology, roughly described, in which a semiconductor structure includes a substrate supporting a column of at least one (and preferably more than one) horizontally-oriented nanosheet transistor, each having a respective channel segment of semiconductor crystalline nanosheet material (preferably silicon or a silicon alloy) sheathed by gate stack material, wherein the channel segments have a…
SYSTEM AND METHOD FOR POWER ANALYSIS FOR DESIGN LOGIC CIRCUIT WITH IRREGULAR CLOCK
Granted: November 19, 2020
Application Number:
20200364391
A system is disclosed that includes a memory and a processor configured to perform operations stored in the memory. The processor performs the operations to select a master clock for a plurality of clocks in a design logic circuit. The processor further performs the operations to align a clock edge of a clock of the plurality of clocks with a corresponding nearest clock transition of the master clock. The aligned clock edge of the clock limits a number of emulation cycles for the design…
Parallel Port Enablement in Pseudo-Dual-Port Memory Designs
Granted: October 15, 2020
Application Number:
20200327932
A pseudo-dual-port memory (PDPM) is disclosed that includes a first memory array bank and a second memory array bank of a plurality of memory array banks. The PDPM also includes parallel pin control logic circuitry configured to perform operations including taking a clock signal, a memory enable signal for a first port, a memory enable signal for a second port, a parallel pin control signal, and address signals for the first and the second memory array banks as inputs and generating a…
Method to Regulate Clock Frequencies of Hybrid Electronic Systems
Granted: September 24, 2020
Application Number:
20200302103
A hybrid electronic system including an emulator side including a processor and a first clock, a simulated side including one or more models to simulate one or more prototypes and a second clock, a first interface to the emulator side, and a second interface to the simulated side is disclosed. The processor is configured to determine using the first interface a first amount of time corresponding to an amount of time advanced on the emulator side by the first clock. The processor is…
Phantom Object Reporting in a Power-and-Ground Router
Granted: August 6, 2020
Application Number:
20200252227
A method to report a phantom object for a structure in a power-and-ground (PG) router is disclosed. The method includes generating the structure of a PG network based on a spec received as input, identifying a violation of a design rule for the structure, and changing the structure to remove the violation of the design rule. The method further includes generating a report of the violation and the changing, generating a phantom object based on the changing, and outputting the report and…
Method and Apparatus for USB Periodic Scheduling Optimization
Granted: June 25, 2020
Application Number:
20200201800
A computerized system is disclosed. The computerized system may include one or more processors configured to perform the operations stored in a memory. The operations may include sorting a subset of a plurality of endpoints for communication during a communication frame first based on service interval time assigned to each endpoint and then resorting based on a concurrency score of each peripheral device corresponding to the subset of the plurality of endpoints. The operations may…
REAL-TIME INTERACTIVE ROUTING USING TOPOLOGY-DRIVEN LINE PROBING
Granted: June 25, 2020
Application Number:
20200202064
Techniques and systems for determining a route from a start point to a target point in an integrated circuit (IC) design using topology-driven line probing are described. Some embodiments can create a data structure to store a set of nodes, wherein each node is located on a horizontal probe or a vertical probe, and wherein each node has a cost. The embodiments can then perform a set of operations in an iterative loop, the set of operations comprising: selecting a lowest cost node from…
EXTENSIBLE LAYER MAPPING FOR IN-DESIGN VERIFICATION
Granted: June 25, 2020
Application Number:
20200202061
Techniques and systems for implementing a general extensible layer mapping approach that maps between integrated circuit (IC) design database layers and process layers are described. A first IC design layout having in-design layers can be converted into a second IC design layout having derived layers, wherein said converting comprises mapping the in-design layers to the derived layers by applying a set of layer derivation rules to shapes in the IC design layout, and wherein the set of…
