CACHED SYSTEM FOR MANAGING STATE VECTORS
Granted: January 4, 2024
Application Number:
20240004794
A cache system includes a computational cache and a computational cache miss-handler. The computational cache is configured to cache state vectors and perform read-modify-write (RMW) operations on the cached state vectors responsive to received RMW commands. The computational cache miss-handler is configured to perform RMW operations on state vectors stored in a memory responsive to cache misses in the computational cache. The memory is external to the cache system.
HARDWARE ACCELERATION OF MACHINE LEARNING DESIGNS
Granted: December 14, 2023
Application Number:
20230401480
Hardware acceleration of machine learning (ML) designs includes translating an ML primitive into an intermediate representation. The intermediate representation is subdivided to specify a functional compute block. The functional compute block is sized according to a compute node primitive adapted for implementing the ML primitive on target hardware. An overlay is generated for the ML primitive, at least in part, by mapping the functional compute block to the compute node primitive. The…
DATAFLOW-BASED COMPUTER PROGRAM VISUALIZATION AND REFACTORING
Granted: December 14, 2023
Application Number:
20230401043
A computer-based visualization and refactoring system is capable of analyzing a computer program to determine computation tasks of the computer program and channels linking the computation tasks. The system generates, in a memory of computer hardware, a dataflow graph having nodes representing the computation tasks and edges representing the channels. The edges connect the nodes. Source code representations of the computation tasks are determined. Execution metrics of the computer…
SPLITTING VECTOR PROCESSING LOOPS WITH AN UNKNOWN TRIP COUNT
Granted: November 30, 2023
Application Number:
20230385040
A computer-based technique for processing an application includes determining that a loop of the application includes a reference to a data item of a vector data type. A trip count of the loop is determined to have an unknown trip count. The loop is split into a first loop and a second loop based on a splitting factor. The second loop is unrolled.
CIRCUIT SIMULATION BASED ON AN RTL COMPONENT IN COMBINATION WITH BEHAVIORAL COMPONENTS
Granted: November 23, 2023
Application Number:
20230376662
Methods and systems for simulating RTL models in combination with behavioral models involve generating an overall simulation model from a circuit design by a simulation tool of an EDA system. The overall simulation model includes respective behavioral simulation models of components of the circuit design. A register transfer level (RTL) simulation model of a particular component of the components of the circuit design is generated by an extractor tool of the EDA system. The respective…
DATA PROCESSING ARRAY INTERFACE HAVING INTERFACE TILES WITH MULTIPLE DIRECT MEMORY ACCESS CIRCUITS
Granted: November 23, 2023
Application Number:
20230376437
An integrated circuit (IC) can include a data processing array including a plurality of compute tiles arranged in a grid. The IC can include an array interface coupled to the data processing array. The array interface includes a plurality of interface tiles. Each interface tile includes a plurality of direct memory access circuits. The IC can include a network-on-chip (NoC) coupled to the array interface. Each direct memory access circuit is communicatively linked to the NoC via an…
NETWORK-ON-CHIP ARCHITECTURE FOR HANDLING DIFFERENT DATA SIZES
Granted: November 16, 2023
Application Number:
20230370392
An integrated circuit (IC) includes a Network-on-Chip (NoC). The NoC includes a plurality of NoC master circuits, a plurality of NoC slave circuits, and a plurality of switches. The plurality of switches are interconnected and communicatively link the plurality of NoC master circuits with the plurality of NoC slave circuits. The plurality of switches are configured to receive data of different widths during operation and implement different operating modes for forwarding the data based…
FRAMEWORK FOR SYSTEM SIMULATION USING MULTIPLE SIMULATORS
Granted: November 16, 2023
Application Number:
20230367923
A simulation framework is capable modeling a hardware implementation of a reference software system using models specified in different computer-readable languages. The models correspond to different ones of a plurality of subsystems of the hardware implementation. Input data is provided to a first simulator configured to simulate a first model of a first subsystem of the modeled hardware implementation. The input data is captured from execution of the reference software system. The…
DEADLOCK DETECTION AND PREVENTION FOR ROUTING PACKET-SWITCHED NETS IN ELECTRONIC SYSTEMS
Granted: November 9, 2023
Application Number:
20230359801
Routing a circuit design includes generating a graph of the circuit design where each connected component is represented as a vertex, generating a routing solution for the circuit design by routing packet-switched nets so that the packet-switched nets of a same connected component do not overlap, and, for each routing resource that is shared by packet-switched nets of different connected components, indicating the shared routing resource on the graph by adding an edge. Cycle detection…
HIGH-THROUGHPUT REGULAR EXPRESSION PROCESSING WITH PATH PRIORITIES USING AN INTEGRATED CIRCUIT
Granted: October 26, 2023
Application Number:
20230342304
A system includes a multi-port RAM configured to store an instruction table. The instruction table specifies a regular expression for application to a data stream. The system includes a regular expression engine (engine) that processes the data stream using the instruction table. The engine includes a decoder circuit that determines validity of active states output from the multi-port RAM and a plurality of priority FIFO memories (PFIFOs) operating concurrently. Each PFIFO can initiate a…
HIGH-THROUGHPUT REGULAR EXPRESSION PROCESSING USING AN INTEGRATED CIRCUIT
Granted: October 26, 2023
Application Number:
20230342068
A system includes a multi-port random-access memory (RAM) configured to store an instruction table. The instruction table specifies a regular expression for application to a data stream. The system includes a regular expression engine configured to process the data stream based on the instruction table. The regular expression engine includes a decoder circuit configured to determine validity of active states output from the RAM, a plurality of active states memories operating…
HIGH-THROUGHPUT REGULAR EXPRESSION PROCESSING WITH CAPTURE USING AN INTEGRATED CIRCUIT
Granted: October 26, 2023
Application Number:
20230342030
A system includes a first multi-port RAM storing an instruction table. The instruction table specifies a regular expression for application to a data stream and a second multi-port RAM configured to store a capture table having capture entries decodable for tracking position information for a sequence of characters matching a capture sub-expression of the regular expression. The system includes a regular expression engine processing the data stream to determine match states by tracking…
MULTIPLE PARTITIONS IN A DATA PROCESSING ARRAY
Granted: October 19, 2023
Application Number:
20230336179
An apparatus includes a data processing array having a plurality of array tiles. Each array tile can include a random-access memory (RAM) having a local memory interface accessible by circuitry within the array tile and an adjacent memory interface accessible by circuitry disposed within an adjacent array tile. Each adjacent memory interface of each array tile can include isolation logic that is programmable to allow the circuitry disposed within the adjacent array tile to access the RAM…
PREDICTING A PERFORMANCE METRIC BASED ON FEATURES OF A CIRCUIT DESIGN AND EXPLAINING MARGINAL CONTRIBUTIONS OF THE FEATURES TO THE PREDICTION
Granted: October 19, 2023
Application Number:
20230334205
A design tool determines features of a circuit design and applies a first model to the features. The first model indicates a predicted value of a metric based on the plurality of features. The design tool applies an explanation model to the features, and the explanation model indicates levels of contributions by the features to the predicted value of the metric, respectively. The design tool selects a feature of the plurality of features based on the respective levels of contributions…
TIME-DIVISION MULTIPLEXING (TDM) IN INTEGRATED CIRCUITS FOR ROUTABILITY AND RUNTIME ENHANCEMENT
Granted: October 5, 2023
Application Number:
20230318921
Implementing a circuit design using time-division multiplexing (TDM) can include determining a net signature for each of a plurality of nets of a circuit design. For each net, the net signature specifies location information for a driver and one or more loads of the net. The plurality of nets having a same net signature can be grouped according to distance between drivers of the respective nets. One or more subgroups can be generated based on a TDM ratio for each group. For one or more…
STATIC AND AUTOMATIC INFERENCE OF INTER-BASIC BLOCK BURST TRANSFERS FOR HIGH-LEVEL SYNTHESIS
Granted: September 28, 2023
Application Number:
20230305949
Static and automatic realization of inter-basic block burst transfers for high-level synthesis can include generating an intermediate representation of a design specified in a high-level programming language, wherein the intermediate representation is specified as a control flow graph, and detecting a plurality of basic blocks in the control flow graph. A determination can be made that plurality of basic blocks represent a plurality of consecutive memory accesses. A sequential access…
PROGRAMMABLE NON-LINEAR ACTIVATION ENGINE FOR NEURAL NETWORK ACCELERATION
Granted: September 21, 2023
Application Number:
20230297824
A programmable, non-linear (PNL) activation engine for a neural network is capable of receiving input data within a circuit. In response to receiving an instruction corresponding to the input data, the PNL activation engine is capable of selecting a first non-linear activation function from a plurality of non-linear activation functions by decoding the instruction. The PNL activation engine is capable of fetching a first set of coefficients corresponding to the first non-linear…
PROGRAMMABLE NON-LINEAR ACTIVATION ENGINE FOR NEURAL NETWORK ACCELERATION
Granted: September 21, 2023
Application Number:
20230297824
A programmable, non-linear (PNL) activation engine for a neural network is capable of receiving input data within a circuit. In response to receiving an instruction corresponding to the input data, the PNL activation engine is capable of selecting a first non-linear activation function from a plurality of non-linear activation functions by decoding the instruction. The PNL activation engine is capable of fetching a first set of coefficients corresponding to the first non-linear…
MULTI-DIE INTEGRATED CIRCUIT WITH DATA PROCESSING ENGINE ARRAY
Granted: September 14, 2023
Application Number:
20230289311
An integrated circuit includes an interposer and a die coupled to the interposer. The die includes a first data processing engine (DPE) array and a second DPE array. The first DPE array includes a first plurality of DPEs and a first DPE interface coupled to the first plurality of DPEs. The second DPE array includes a second plurality of DPEs and a second DPE interface coupled to the second plurality of DPEs. The integrated circuit includes one or more other dies having a first die…
ADAPTIVE INTEGRATED PROGRAMMABLE DEVICE PLATFORM
Granted: September 14, 2023
Application Number:
20230291405
A System-on-Chip includes a data processing engine array. The data processing engine array includes a plurality of data processing engines organized in a grid. The plurality of data processing engines are partitioned into at least a first partition and a second partition. The first partition includes one or more first data processing engines of the plurality of data processing engines. The second partition includes one or more second data processing engines of the plurality of data…
