ADAPTIVE INTEGRATED PROGRAMMABLE DEVICE PLATFORM
Granted: September 14, 2023
Application Number:
20230291405
A System-on-Chip includes a data processing engine array. The data processing engine array includes a plurality of data processing engines organized in a grid. The plurality of data processing engines are partitioned into at least a first partition and a second partition. The first partition includes one or more first data processing engines of the plurality of data processing engines. The second partition includes one or more second data processing engines of the plurality of data…
SELECTION OF FULL OR INCREMENTAL IMPLEMENTATION FLOWS IN PROCESSING CIRCUIT DESIGNS
Granted: September 14, 2023
Application Number:
20230289503
A machine learning-based process includes identifying a first set of features that includes features of a reference implementation of a circuit design and features of a synthesized version of a modified version of the circuit design. A first classification model is applied to the first set of features, and the first classification model indicates a full implementation flow or an incremental implementation flow. The full implementation flow is performed on the synthesized version of the…
METHOD AND SYSTEM FOR BUILDING HARDWARE IMAGES FROM HETEROGENEOUS DESIGNS FOR ELETRONIC SYSTEMS
Granted: September 14, 2023
Application Number:
20230289500
Automatically generating a hardware image based on programming model types includes determining by a design tool, types of programming models used in specifications of blocks of a circuit design, in response to a user control input to generate a hardware image to configure a programmable integrated circuit (IC). The design tool can generate a model-type compiler script for each of the types of programming models. Each compiler script initiates compilation of blocks having specifications…
MULTI-DIE INTEGRATED CIRCUIT WITH DATA PROCESSING ENGINE ARRAY
Granted: September 14, 2023
Application Number:
20230289311
An integrated circuit includes an interposer and a die coupled to the interposer. The die includes a first data processing engine (DPE) array and a second DPE array. The first DPE array includes a first plurality of DPEs and a first DPE interface coupled to the first plurality of DPEs. The second DPE array includes a second plurality of DPEs and a second DPE interface coupled to the second plurality of DPEs. The integrated circuit includes one or more other dies having a first die…
SPARSE MATRIX DENSE VECTOR MULTLIPLICATION CIRCUITRY
Granted: August 24, 2023
Application Number:
20230267169
Circuitry for multiplying a sparse matrix by a dense vector includes a first switching circuit (302) for routing input triplets from N input ports to N output ports based on column indices of the triplets. Each triplet includes a non-zero value, a row index, and a column index. N first memory banks (303) store subsets of vector elements and are addressed by the column indices of the triplets. N multipliers (305) multiply the non-zero values of the triplets by the vector element read from…
EXTENSIBLE DEVICE HOSTED ROOT OF TRUST ARCHITECTURE FOR INTEGRATED CIRCUITS
Granted: August 17, 2023
Application Number:
20230259627
An integrated circuit can include a communication endpoint configured to maintain a communication link with a host computer, a queue configured to receive a plurality of host commands from the host computer via the communication link, and a processor configured to execute a device runtime. The processor, responsive to executing the device runtime, is configured to perform validation of the host commands read from the queue and selectively execute the host commands based on a result of…
TESTBENCH FOR SUB-DESIGN VERIFICATION
Granted: August 10, 2023
Application Number:
20230252212
Testbench creation for sub-design verification can include receiving, using computer hardware, a selection of a sub-design of a circuit design. The sub-design is one of a plurality of sub-designs of the circuit design. The circuit design includes a plurality of parameter values. A list of port-level signal information is generated for the selected sub-design. The one or more parameter values of the circuit design are extracted. Switching activity of each port-level signal from the list…
NEURAL NETWORK PROCESSING OF REORDERED COLOR FILTER ARRAY FORMATTED IMAGE DATA
Granted: August 3, 2023
Application Number:
20230245269
A rearranger circuit rearranges data elements of each raw image of a plurality of raw images according to a plurality of raw color channel arrays. The data elements of each raw image are input to the rearranger circuit according to instances of a pattern of color channels of a color filter array (CFA). The data elements specify values of the color channels in the instances of the pattern, and each raw color channel array has the data elements of one color channel of the color channels in…
MACHINE LEARNING DEPLOYMENT PLATFORM
Granted: August 3, 2023
Application Number:
20230244966
An inference server is capable of receiving a plurality of inference requests from one or more client systems. Each inference request specifies one of a plurality of different endpoints. The inference server can generate a plurality of batches each including one or more of the plurality of inference requests directed to a same endpoint. The inference server also can process the plurality of batches using a plurality of workers executing in an execution layer therein. Each batch is…
TRANSPARENT AND REMOTE KERNEL EXECUTION IN A HETEROGENEOUS COMPUTING SYSTEM
Granted: July 20, 2023
Application Number:
20230229497
Remote kernel execution in a heterogeneous computing system can include executing, using a device processor of a device communicatively linked to a host processor, a device runtime and receiving from the host processor within a hardware submission queue of the device, a command. The command requests execution of a software kernel and specifies a descriptor stored in a region of a memory of the device shared with the host processor. In response to receiving the command, the device…
HYBRID SYNCHRONOUS AND ASYNCHRONOUS CONTROL FOR SCAN-BASED TESTING
Granted: June 29, 2023
Application Number:
20230205959
An integrated circuit includes an intellectual property core, scan data pipeline circuitry configured to convey scan data to the intellectual property core, and scan control pipeline circuitry configured to convey one or more scan control signals to the intellectual property core. The integrated circuit also includes a wave shaping circuit configured to detect a trigger event on the one or more scan control signals and, in response to detecting the trigger event, suppress a scan clock to…
CIRCULAR BUFFER ARCHITECTURE USING LOCAL MEMORIES WITH LIMITED RESOURCES
Granted: June 29, 2023
Application Number:
20230205452
A circular buffer architecture includes a memory coupled to a producer circuit and a consumer circuit. The memory is configured to store objects. The memory can include memory banks. The number of the memory banks is less than a number of the objects. The circular buffer can include hardware locks configured to reserve selected ones of the memory banks for use by the producer circuit or the consumer circuit. The circular buffer can include a buffer controller coupled to the memory and…
APPLICATION IMPLEMENTATION AND BUFFER ALLOCATION FOR A DATA PROCESSING ENGINE ARRAY
Granted: June 15, 2023
Application Number:
20230185548
Implementing an application can include generating, from the application, a compact data flow graph (DFG) including load nodes, inserting, in the compact DFG, a plurality of virtual buffer nodes (VBNs) for each of a plurality of buffers of a data processing engine (DPE) array to be allocated to nets of the application, and, forming groups of one or more load nodes of the compact DFG based on shared buffer requirements of the loads on a per net basis. Virtual driver nodes (VDNs) that map…
COMPRESSION OF SPARSE TENSORS
Granted: June 15, 2023
Application Number:
20230185451
Approaches for data compression involve a compression circuit packing non-zero data elements of a succession of words of a plurality of blocks into packed words by packing non-zero data elements of one or more words of the succession in each packed word, and restricting each packed word to data elements of one uncompressed block. The compression circuit writes each packed word in a RAM and within a compressed address range associated with the uncompressed block when the packed word is…
PIPELINED PROCESSING OF POLYNOMIAL COMPUTATION
Granted: June 8, 2023
Application Number:
20230176819
Circuits and methods for computing an order N polynomial include V decimation stages, each stage including respective multiply-and-accumulate circuitry. The multiply-and-accumulate circuitry in each stage k, in response to an input r-term and a plurality of input z-terms 0 through (Nk?1), generates output z-terms 0 through (Nk/2?1) and an output r-term as a square of the input r-term. Each output z-term i is a sum of input z-term (2i+1) of the input z-terms and a product of input z-term…
METHOD AND SYSTEM FOR INTERFACING A TESTBENCH TO CIRCUIT SIMULATION
Granted: June 1, 2023
Application Number:
20230169226
Approaches for simulating a circuit include receiving simulation input data from a testbench executing on a computer system by a simulator interface executing on the computer system. The simulator interface receives simulation output data the according to a hardware bus protocol specified by a simulated circuit for communication and simulates handshaking with the simulated circuit according to the hardware bus protocol in response to receiving the simulation input data and simulation…
COMPILATION OF NEURAL NETWORKS INTO SUBGRAPHS FOR PROCESSING BY MULTIPLE COMPUTE CIRCUITS
Granted: May 18, 2023
Application Number:
20230153583
Processing of a neural network specification includes gathering first layers of a neural network graph into groups of layers based on profiled compute times of the layers and equalized compute times between the groups. Each group is a subgraph of one or more of the layers of the neural network. The neural network graph is compiled into instructions for pipelined execution of the neural network graph by compute circuits. The compiling includes designating, for each first subgraph of the…
PROTOCOL AWARE BRIDGE CIRCUIT FOR LOW LATENCY COMMUNICATION AMONG INTEGRATED CIRCUITS
Granted: May 18, 2023
Application Number:
20230153260
A system includes a bridge circuit configured for low latency communication among integrated circuits (ICs). The bridge circuit includes a plurality of transceiver circuits. Each transceiver circuit is coupled to a corresponding parallel channel in the IC. Each transceiver circuit is configured to send and receive data over the corresponding parallel channel. Each transceiver circuit includes a transmit channel configured to packetized data received from the corresponding parallel…
SYNCHRONIZATION OF SYSTEM RESOURCES IN A MULTI-SOCKET DATA PROCESSING SYSTEM
Granted: May 18, 2023
Application Number:
20230153156
Synchronizing system resources of a multi-socket data processing system can include providing, from a primary System-on-Chip (SOC), a trigger event to a global synchronization circuit. The primary SOC is one of a plurality of SOCS and the trigger event is provided over a first sideband channel. In response to the trigger event, the global synchronization circuit is capable of broadcasting a synchronization event to the plurality of SOCS over a second sideband channel. In response to the…
DYNAMIC PORT HANDLING FOR ISOLATED MODULES AND DYNAMIC FUNCTION EXCHANGE
Granted: May 11, 2023
Application Number:
20230148419
Dynamic port handling for circuit designs can include inserting, within a static isolated module of a circuit design, static drivers configured to drive isolated modules of reconfigurable module (RM) instances for inclusion in an RM of the circuit design. For each RM instance of a plurality of RM instances to be inserted into the RM, one or more additional ports can be inserted in the RM based on a number of isolated modules included in a current RM instance. Further, net(s)…
