Xilinx Patent Grants

Clock stoppage in integrated circuits with multiple asynchronous clock domains

Granted: March 21, 2017
Patent Number: 9600018
Methods and circuits for performing a clock-stop process of a circuit are disclosed. For example, a circuit includes a clock group having a first clock domain, a first clock multiplexer, a first synchronizer and a controller. The controller is configured to initiate a clock stop process of the circuit by sending an alternative mode signal to the first synchronizer. The first synchronizer is configured to synchronize the alternative mode signal to a clock of the first clock domain and is…

Block-level code coverage in simulation of circuit designs

Granted: March 21, 2017
Patent Number: 9600613
Various example implementations are directed to methods and systems for simulating circuit designs having configuration parameters. According to one example implementation, code blocks of a circuit design for which execution of operations described by the code blocks is conditioned on a value of one or more of a set of configuration parameters, are identified. For each identified code block, a respective expression is determined that indicates whether or not the code block will be…

Offset insensitive quadrature clock error correction and duty cycle calibration for high-speed clocking

Granted: March 21, 2017
Patent Number: 9602082
Techniques for correcting clock distortion. The techniques include use of circuitry for detecting and correcting duty cycle distortion and quadrature clock phase distortion. For phase detection, detection circuitry is made simpler and more accurate through the use of a sampling operation in which device mismatch within detection circuitry is accounted for by sampling charge associated with an ideal clock signal across sampling capacitors. When phase detection is performed with the…

Lut cascading circuit

Granted: March 21, 2017
Patent Number: 9602108
In an example, a LUT for a programmable integrated circuit (IC) includes a plurality of input terminals, and a cascading input coupled to at least one other LUT in the programmable IC. The LUT further includes LUT logic having a plurality of LUTs each coupled to a common set of the input terminals. The LUT further includes a plurality of multiplexers having inputs coupled to outputs of the plurality of LUTs, and an output multiplexer having inputs coupled to outputs of the plurality of…

Circuit for and method of enabling the adaptation of an automatic gain control circuit

Granted: March 14, 2017
Patent Number: 9595990
A circuit for enabling an adaptation of an automatic gain control circuit comprises an automatic gain control (ACG) circuit configured to receive an input signal and to generate a boosted input signal. An average peak signal magnitude adaptation circuit is configured to receive an output of a decision circuit and to generate an average peak signal magnitude. An average peak signal target calculation circuit is configured to receive the average peak signal magnitude and detected peak…

Partitioning memory in programmable integrated circuits

Granted: March 7, 2017
Patent Number: 9589088
Various example implementations are directed to circuits and methods for partitioning a memory for a circuit design in a programmable IC. A user interface is provided for a user to define subsystems, master circuits, memory segments, and permissions for accessing the memory segments by the master circuits. For each defined memory segment, a respective access control entry is generated that includes data for determining master circuits that are permitted access to the memory segment by…

Moving mean and magnitude dual path digital predistortion

Granted: March 7, 2017
Patent Number: 9590567
An apparatus relates generally to preconditioning an input signal. In this apparatus, a first digital predistortion module and a second digital predistortion module are for receiving the input signal for respectively providing a first predistorted signal and a second predistorted signal. A combiner is for combining the first predistorted signal and the second predistorted signal for providing an output signal. The first digital predistortion module includes a moving mean block for…

Methods and circuits for testing partial circuit designs

Granted: February 28, 2017
Patent Number: 9581643
Methods and circuits are disclosed for testing a partial circuit design including circuit modules having a set of ports configured to be driven by signals from ports of one or more circuits omitted from the partial circuit. The set of ports are identified by identifying ports that are not connected by a net to another port or input/output (I/O) pin in the circuit design and that form inputs to slave circuits in the circuit modules. A traffic generator circuit is added to the partial…

Simulation of a circuit design block using pattern matching

Granted: February 28, 2017
Patent Number: 9582619
An approach for simulating a block of a circuit design includes using a row-matching table and a port state vector. The row-matching table includes a plurality of rows, and each row includes encoded input match patterns corresponding to a plurality of input ports of the block and an associated output value. The port state vector includes input state codes associated with the input ports. In response to an update of an input signal value at one of the input ports during simulation, the…

Asynchronous clock generation for time-interleaved successive approximation analog to digital converters

Granted: February 28, 2017
Patent Number: 9584144
A clock generator includes: a first input to receive a global clock signal; a second input to receive a completion signal; a third input to receive differential outputs in a conversion cycle from a comparator; and a logic circuit configured to generate a control clock signal based at least in part on the global clock signal and the differential outputs, and to provide the control clock signal to the comparator for a next conversion cycle; and wherein the logic circuit is also configured…

Circuit for and method of compensating for mismatch in a time-interleaved analog-to-digital converter

Granted: February 28, 2017
Patent Number: 9584145
A circuit for compensating for mismatch in a plurality of channels of a time-interleaved analog-to-digital converter is described. The circuit comprises an analog-to-digital converter circuit of a first channel of the plurality of channels configured to receive an analog input signal and to generate a digital value associated with the analog input signal; an arithmetic circuit configured to receive the digital value generated at the output of the analog-to-digital converter; a memory…

Physically unclonable function and helper data indicating unstable bits

Granted: February 28, 2017
Patent Number: 9584329
Approaches for using a physically unclonable function (PUF) are described. A selector map is used to indicate stable and unstable bits in a PUF value that is generated by a PUF circuit. The stable bits of the PUF value generated by the PUF circuit may be selected for use by an application, and the unstable bits ignored.

On chip detection of electrical overstress events

Granted: February 21, 2017
Patent Number: 9575111
A system configured for detecting electrical overstress events within an integrated circuit includes a comparator configured to determine whether a monitored voltage level of a monitored signal exceeds an overstress reference voltage level. The overstress reference voltage level is a predetermined amount of voltage above a nominal voltage level for the monitored signal. The system further includes a write circuit coupled to an output of the comparator. The write circuit is configured to…

Circuits for and methods of reducing duty-cycle distortion in an integrated circuit implementing dual-edge clocking

Granted: February 21, 2017
Patent Number: 9577615
A circuit for reducing duty-cycle distortion in an integrated circuit implementing dual-edge clocking is described. The circuit also comprises a plurality of circuit elements that enable the routing of data generated at outputs of the circuit elements; a plurality of register circuits that store data at outputs of the plurality of circuit elements; a clock circuit routing a clock signal to clock inputs of the plurality of register circuits; and a pulsed-controlled register circuit…

High-speed serial data interface for a physical layer interface

Granted: January 31, 2017
Patent Number: 9557766
In an apparatus relating generally to the communication of data, a first and a second receive path block are respectively coupled to receive a first and a second data stream. A clock signal source is coupled to provide at least one clock signal to each of the first and the second receive path block. A control block is coupled to receive a first output signal pair and a second output signal pair from the first and the second receive path block, respectively. The first output signal pair…

Multiprocessor system with performance control based on input and output data rates

Granted: January 31, 2017
Patent Number: 9557795
A multi-processor system with dynamic power optimization for an integrated circuit and methods thereof are described. An input rate control signal is generated responsive to at least one input data stream. An output rate control signal is generated responsive to an output of the plurality of processors. The input rate control signal and the output rate control signal are monitored. The at least one input data stream is partitioned in response to the input rate control signal. The…

Circuits for and methods of enabling the access to data

Granted: January 31, 2017
Patent Number: 9558129
A circuit for enabling access to data is described. The circuit comprises a memory device storing data blocks having a first predetermined size; and a direct memory access circuit coupled to the memory device, the direct memory circuit accessing a data payload having a second predetermined size which is greater than the first predetermined size; wherein the direct memory access circuit accesses the data payload in response to a descriptor having a plurality of addresses corresponding to…

Adaptive video direct memory access module

Granted: January 31, 2017
Patent Number: 9558528
A method, computing device, and non-transitory computer-readable medium for arbitrating data for channels in a video pipeline. The method includes determining arbitration weights for the channels. The method also includes determining which channels have arbitration weights above a threshold. The method further includes issuing data to the channels with arbitration weights above the threshold. The method also includes decrementing arbitration weights for channels for which data is issued.…

Circuits for and methods of generating clock signals enabling the latching of data in an integrated circuit

Granted: January 31, 2017
Patent Number: 9559669
A circuit for generating clock signals enabling the latching of data is described. The circuit comprises a pulse generator coupled to receive an input clock signal at an input and to generate an output clock signal at an output; a latch circuit coupled to receive the output clock signal; and a pulse shaping circuit coupled to receive a feedback signal; wherein a pulse width of the output clock signal is determined by the feedback signal and the input signal coupled to the pulse…

Fractional-N phase-locked loop with reduced jitter

Granted: January 31, 2017
Patent Number: 9559704
In an example, operating a PLL circuit includes generating an error signal in response to comparison of a reference clock signal having a reference frequency and a feedback clock signal having a feedback frequency, generating a plurality of clock signals having an output frequency based on the error signal, and generating the feedback clock signal from the plurality of clock signals based on a first divider value and a control value derived from a second divider value. Operating the PLL…