Xilinx Patent Grants

Rate controlled buffer for output at either a first or second rate responsive to a fill level

Granted: May 23, 2017
Patent Number: 9658822
Buffer rate control generally relates to outputting data at either a first rate or a second rate responsive to a fill level of the buffer. In an apparatus therefore, there is a buffer for receiving a data-signal input and for providing a data-signal output. A controller is coupled to receive fill-level information from the buffer and coupled to provide rate-control information to the buffer. The rate-control information is for controlling an output rate of the buffer for the data-signal…

Multi-threaded low-level startup for system boot efficiency

Granted: May 23, 2017
Patent Number: 9658858
Methods, computer-readable media and devices for executing a plurality of startup instructions are disclosed. For example, a method includes a first processor of a device accessing a plurality of startup instructions in response to a startup of the device. The first processor then executes a first startup instruction of the plurality of startup instructions to perform a first task and executes a second startup instruction of the plurality of startup instructions. The executing the second…

System and method for power based selection of boot images

Granted: May 16, 2017
Patent Number: 9652252
Circuits and methods for power dependent selection of boot images are disclosed. In an example implementation, an apparatus includes a memory circuit and a processor disposed on an integrated circuit die. The processor is configured to retrieve and execute instructions from the memory circuit. The apparatus also includes a power management circuit configured to determine a value indicative of an amount of power available to power the IC die. A boot loader circuit is coupled to the power…

Automated modification of configuration settings of an integrated circuit

Granted: May 16, 2017
Patent Number: 9652410
Automated modification of configuration settings for an IC (IC) includes receiving, within a data processing system, desired data for a configuration setting of an IC, reading stored data for the configuration setting. A determination is made using the data processing system that the configuration setting is static and that the stored data differs from the desired data. Responsive to the determination, configuration data including the desired data is provided from the data processing…

Automatic implementation of a customized system-on-chip

Granted: May 16, 2017
Patent Number: 9652570
Implementing a system-on-chip (SOC) design specified as a high level programming language (HLL) application may include querying, using a computer, a platform description to determine an available interface of a platform for a target integrated circuit and generating, using the computer, hardware for a function of the HLL application marked for hardware acceleration and hardware coupling the marked function with the available interface of the platform. Implementing the SOC design may…

Multiplexer-based ternary content addressable memory

Granted: May 16, 2017
Patent Number: 9653165
In one example, a ternary content addressable memory (TCAM) includes an input port coupled to receive a W-bit key as input, and an output port coupled to provide a match vector as output, the match vector including at least one bit. The TCAM further includes a memory having memory cells operable to store N*W pairs of bits for N W-bit TCAM words. The memory includes a plurality of memory outputs. The TCAM further includes at least one compare circuit. The at least one compare circuit…

Channel adaptive ADC-based receiver

Granted: May 16, 2017
Patent Number: 9654327
A receiver relates generally to channel adaptation. In this receiver, a first signal processing block is coupled to a communications channel. The first signal processing block includes: an AGC block and a CTLE block for receiving a modulated signal for providing an analog signal; an ADC for converting the analog signal to digital samples; and an FFE block for equalizing the digital samples to provide equalized samples. A second signal processing block includes: a DFE block for receiving…

Linking of simulators into a circuit design tool

Granted: May 9, 2017
Patent Number: 9646118
Simulators are linked to a circuit design tool by establishing a plurality of simulator objects in response to a plurality of registration commands, respectively. Each registration command specifies a simulation interface application associated with one of the simulators, and the simulation interface application has procedures for initiating functions of the associated simulator. For each simulator, values of properties of the simulator are stored in the respective simulator object. The…

Post-routing structural netlist optimization for circuit designs

Granted: May 9, 2017
Patent Number: 9646126
Post-routing processing of a circuit design may include determining, using a processor, a baseline delay for a path of a routed circuit design, comparing, using the processor, the baseline delay of the path with a timing constraint of the path, and selectively applying, according to the comparing, a structural netlist optimization to the path resulting in an optimized path using a processor.

Generation of delay values for a simulation model of circuit elements in a clock network

Granted: May 2, 2017
Patent Number: 9639640
An approach for generating delay values for circuit elements in a clock network of a programmable IC includes determining for each clock resource in the clock network, different possible contexts of the clock resource. Each context specifies a combination of possible types of circuit elements in the context. Circuit elements of the possible types are selected from the different contexts, and configuration data is generated for implementation of respective ring oscillator circuits that…

System-on-chip intellectual property block discovery

Granted: May 2, 2017
Patent Number: 9639646
An integrated circuit (IC) includes a bridge circuit configured to receive a first request from an external system, a discover circuit coupled to the bridge circuit and configured to process the first request received from the bridge circuit, and a memory map coupled to the discover circuit. The memory map stores a record for each of a plurality of Intellectual Property (IP) blocks implemented within the IC. The discover circuit is configured to generate a list of the IP blocks…

Error correction for interconnect circuits

Granted: April 25, 2017
Patent Number: 9632869
In approaches for correction of errors introduced in an interconnect circuit, an ECC proxy circuit is coupled between a first interconnect and the second interconnect, and generates for each of the write transactions from a bus master circuit, a first ECC from and associated with data of the write transaction, and transmits the write transaction and associated first ECC on the second interconnect. The ECC proxy circuit also supplements each of the read transactions from the bus master…

Trimming a temperature dependent voltage reference

Granted: April 25, 2017
Patent Number: 9634648
A circuit includes a divider circuit block configured to generate a trim term signal (VBG_TRIM) that is temperature and process independent. The circuit further includes a processing circuit block configured to multiply a temperature dependent reference voltage signal (TAP_GG) by a factor, and to sum the trim term signal with a result of the multiplication to generate an output reference voltage (VGG).

Visualizing transactions of a transaction-based system

Granted: April 18, 2017
Patent Number: 9626780
Visualizing transactions in a transaction-based system includes displaying, on a display device, an x-y coordinate system including an x-axis and a y-axis, wherein the x-axis is demarcated in units of time and the y-axis is demarcated according to a transaction characteristic and formatting, using a processor, each of a plurality of transactions of a transaction system as a line having a start end representing a start of the transaction and a terminating end representing an end of the…

Multi-chip integrated circuit

Granted: April 18, 2017
Patent Number: 9627261
An integrated circuit (IC) combines a first IC chip (die) having a first on-chip interconnect structure and a second IC chip having a second on-chip interconnect structure on a reconstructed wafer base. The second IC chip is edge-bonded to the first IC chip with oxide-to-oxide edge bonding. A chip-to-chip interconnect structure electrically couples the first IC chip and the second IC chip.

Interposer with edge reinforcement and method for manufacturing same

Granted: April 18, 2017
Patent Number: 9627329
A TSV interposer having a reinforced edge and methods for fabricating an IC package utilizing the same are provided. In one embodiment, a chip package includes an interposer having a wiring layer and a die disposed on a surface of the interposer. The die is electrically connected to the wiring layer of the interposer. A die underfill material is disposed between the interposer and the die. The die underfill material at least partially covers a side of the die that extends away from the…

Interconnect circuits having low threshold voltage P-channel transistors for a programmable integrated circuit

Granted: April 18, 2017
Patent Number: 9628081
An exemplary interconnect circuit for a programmable integrated circuit (IC) includes an input terminal coupled to receive from a node in the programmable IC, an output terminal coupled to transmit towards another node in the programmable IC, first and second control terminals coupled to receive from a memory cell of the programmable IC, and a complementary metal oxide semiconductor (CMOS) pass-gate coupled between the input terminal and the output terminal and to the first and second…

Strength-adjustable driver

Granted: April 18, 2017
Patent Number: 9628082
An apparatus includes a plurality of adjustable driver circuits having output nodes coupled to a signal line. Each adjustable driver circuit is configured to drive the signal line with a portion of a total drive strength indicated by a value of a binary control signal. The apparatus also includes a delay circuit configured to delay the binary control signal provided to each adjustable driver circuit by a respective time period unique to the adjustable driver circuit.

Control and data flow graph generation for hardware description languages

Granted: April 11, 2017
Patent Number: 9619601
An example method of generating a control and data flow graph for hardware description language (HDL) code specifying a circuit design is described. The method includes traversing an abstract syntax tree (AST) representation of the HDL code having a plurality of modules on a module-by-module basis. The method further includes adding an execution unit to the control and data flow graph for each module having concurrent paths. Each execution unit includes nodes in the control and data flow…

Digital fractional-N multiplying injection locked oscillator

Granted: April 4, 2017
Patent Number: 9614537
An example clock generator circuit includes a fractional reference generator configured to generate a reference clock in response to a base reference clock and a phase error signal, the reference clock having a frequency that is a rational multiple of a frequency of the base reference clock. The clock generator circuit includes a digitally controlled delay line (DCDL) that delays the reference clock based on a first control code, and a pulse generator configured to generate pulses based…