Xilinx Patent Grants

Methods and circuits for debugging circuit designs

Granted: June 13, 2017
Patent Number: 9678150
Various example implementations are directed to circuits and methods for debugging circuit designs. According to an example implementation, waveform data is captured, for a set of signals produced by a circuit design during operation. Data structures are generated for the set of signals and waveform data for the signals is stored in the data structures. Communication channels associated with the set of signals are identified. Waveform data stored in the data structures is analyzed to…

Constraint handling for parameterizable hardware description language

Granted: June 13, 2017
Patent Number: 9679092
Constraint handling for a circuit design may include determining, using a processor, instances of parameterizable modules of a circuit design associated with constraints based upon a predefined hardware description language attribute within the instances, extracting, using the processor, parameter values from the instances of the parameterizable modules, and generating, using the processor, static constraint files for the instances of the parameterizable modules using the extracted…

System and method to reduce footprint and improve yield of fabric muxes in programmable logic devices

Granted: June 13, 2017
Patent Number: 9680474
An interconnect element includes: a selection circuit for receiving input signals and having a selection output; a half-latch circuit having an input coupled to the selection output, wherein the half latch circuit comprises a pull-up device; and a common bias circuit coupled to the pull-up device, wherein the common bias circuit is configured to supply a tunable bias voltage to the pull-up device.

Threshold detection with digital correction in analog to digital converters

Granted: June 13, 2017
Patent Number: 9680492
An analog to digital converter (ADC) includes a comparator and a plurality of capacitor pairs coupled between first and second inputs the comparator, where each one of the capacitor pairs corresponds to one of a plurality of cycles used by the ADC to generate a digital value representing a sampled analog voltage. The ADC also includes a voltage detection circuit and a state machine that is configured to, upon determining during a first cycle that the sampled voltage across the first and…

Interconnect circuitry fault detection

Granted: June 6, 2017
Patent Number: 9672094
Fault detection for an interconnect bus includes performing safety register validation including validating correct operation of a safety register in a slave circuit. The safety register is reserved for validation operations. Write bus validation is performed where, over an address range of the slave circuit, received write addresses within the address range are stored in the safety register of the slave circuit and read back by a master circuit for validation. Read bus validation is…

Circuits for and methods of generating a modulated signal in a transmitter

Granted: June 6, 2017
Patent Number: 9674015
A circuit for generating a modulated signal in a transmitter of an integrated circuit is disclosed. The circuit comprises a transmitter driver circuit having a first current path for receiving a first input signal of a pair of differential input signals and a second current path for receiving a second input signal of the pair of differential input signals, the transmitter driver circuit comprising a tail current path coupled to each of the first current path and the second current path;…

Efficient mapping of table pipelines for software-defined networking (SDN) data plane

Granted: June 6, 2017
Patent Number: 9674081
Methods and apparatus for using dynamic programming to determine the most efficient mapping of a pipeline of virtual flow tables (VFTs) onto a pipeline of physical flow tables (PFTs) in the data plane of a software-defined networking (SDN) device are described. One example method of determining a configuration for an SDN device generally includes receiving a representation of a series of one or more VFTs, each of the VFTs having one or more properties; receiving a representation of a…

Mechanism for inter-processor interrupts in a heterogeneous multiprocessor system

Granted: May 30, 2017
Patent Number: 9665509
Apparatus and methods for handling inter-processor interrupts (IPIs) in a heterogeneous multiprocessor system are provided. The scalable IPI mechanism provided herein entails minimal logic and can be used for heterogeneous inter-processor communication, such as between application processors, real-time processors, and FPGA accelerators. This mechanism is also low cost, in terms of both logic area and programmable complexity. One example system generally includes a first processor, a…

Emulating power gating for a circuit design using a programmable integrated circuit

Granted: May 30, 2017
Patent Number: 9665671
Emulating power gating includes identifying an isolation circuit having a first input coupled to an output of a first power domain, a second input coupled to an isolation signal, and an output coupled to an input of a second power domain; removing a power gate circuit configured to selectively decouple the first power domain from a power supply responsive to a power gate signal; and decoupling the first input of the isolation circuit from the output of the first power domain. A power…

Designing a system for a programmable system-on-chip using performance characterization techniques

Granted: May 30, 2017
Patent Number: 9665683
An example method of implementing a system design for a programmable system-on-chip (SOC) having a processing system and programmable logic includes receiving a description of performance objectives for the system design. The method further includes accessing a characterization database that relates parameter settings of the processing system to performance under different traffic profiles as generated by an emulation system comprising the processing system and one or more circuit blocks…

Secure configuration readback for programmable logic devices

Granted: May 30, 2017
Patent Number: 9666248
A programmable integrated circuit, includes an external port, a configuration memory, a hardened write path between the external port and the configuration memory and a soft read path between the configuration memory and the external port, wherein configuration data stored in the configuration memory is only read through the soft read path.

Power control over memory cell arrays

Granted: May 30, 2017
Patent Number: 9666266
In disclosed circuit arrangements, memory cell arrays are addressed by a first portion of an input address, and memory cells within each memory cell array are addressed by a second portion of the input address. A first first-in-first-out (FIFO) buffer is coupled to the memory cell arrays and delays the second portion of each input address to the memory cell arrays for a sleep period. Control circuits respectively coupled to the memory cell arrays include second FIFO buffers and decode…

Phase interpolator with improved linearity at quadrant boundaries

Granted: May 30, 2017
Patent Number: 9667236
A phase interpolator includes: a digital-to-analog converter to generate bias signals associated with phase signals; a multiplexer having an input interface and an output interface, wherein the digital-to-analog converter is coupled to the input interface of the multiplexer; a first current source; and a second current source; wherein the digital-to-analog converter is configured to provide bleeder current signals to the first current source and the second current source while bypassing…

Efficient low error-floor LDPC codes

Granted: May 30, 2017
Patent Number: 9667276
A system for providing data encoding includes: an encoder configured to encode message data with an encoding parity-check matrix having a parity part that is in lower-triangular form to generate an encoded message data, the encoded message data being for decoded by a decoder; wherein the encoding parity-check matrix is based on a decoding parity-check matrix that does not comprise any degree-1 node in a parity part of the decoding parity-check matrix; and wherein the system further…

Rate controlled buffer for output at either a first or second rate responsive to a fill level

Granted: May 23, 2017
Patent Number: 9658822
Buffer rate control generally relates to outputting data at either a first rate or a second rate responsive to a fill level of the buffer. In an apparatus therefore, there is a buffer for receiving a data-signal input and for providing a data-signal output. A controller is coupled to receive fill-level information from the buffer and coupled to provide rate-control information to the buffer. The rate-control information is for controlling an output rate of the buffer for the data-signal…

Multi-threaded low-level startup for system boot efficiency

Granted: May 23, 2017
Patent Number: 9658858
Methods, computer-readable media and devices for executing a plurality of startup instructions are disclosed. For example, a method includes a first processor of a device accessing a plurality of startup instructions in response to a startup of the device. The first processor then executes a first startup instruction of the plurality of startup instructions to perform a first task and executes a second startup instruction of the plurality of startup instructions. The executing the second…

System and method for power based selection of boot images

Granted: May 16, 2017
Patent Number: 9652252
Circuits and methods for power dependent selection of boot images are disclosed. In an example implementation, an apparatus includes a memory circuit and a processor disposed on an integrated circuit die. The processor is configured to retrieve and execute instructions from the memory circuit. The apparatus also includes a power management circuit configured to determine a value indicative of an amount of power available to power the IC die. A boot loader circuit is coupled to the power…

Automated modification of configuration settings of an integrated circuit

Granted: May 16, 2017
Patent Number: 9652410
Automated modification of configuration settings for an IC (IC) includes receiving, within a data processing system, desired data for a configuration setting of an IC, reading stored data for the configuration setting. A determination is made using the data processing system that the configuration setting is static and that the stored data differs from the desired data. Responsive to the determination, configuration data including the desired data is provided from the data processing…

Multiplexer-based ternary content addressable memory

Granted: May 16, 2017
Patent Number: 9653165
In one example, a ternary content addressable memory (TCAM) includes an input port coupled to receive a W-bit key as input, and an output port coupled to provide a match vector as output, the match vector including at least one bit. The TCAM further includes a memory having memory cells operable to store N*W pairs of bits for N W-bit TCAM words. The memory includes a plurality of memory outputs. The TCAM further includes at least one compare circuit. The at least one compare circuit…

Channel adaptive ADC-based receiver

Granted: May 16, 2017
Patent Number: 9654327
A receiver relates generally to channel adaptation. In this receiver, a first signal processing block is coupled to a communications channel. The first signal processing block includes: an AGC block and a CTLE block for receiving a modulated signal for providing an analog signal; an ADC for converting the analog signal to digital samples; and an FFE block for equalizing the digital samples to provide equalized samples. A second signal processing block includes: a DFE block for receiving…