Xilinx Patent Grants

Phase-locked loop having sampling phase detector

Granted: August 22, 2017
Patent Number: 9742380
An example a phase-locked loop (PLL) circuit includes a sampling phase detector configured to receive a reference clock and a feedback clock and configured to supply a first control current and a pulse signal. The PLL further includes a charge pump configured to generate a second control current based on the first control current and the pulse signal. The PLL further includes a loop filter configured to filter the second control current and generate an oscillator control voltage. The PLL…

Decision feedback equalizer

Granted: August 22, 2017
Patent Number: 9742597
An apparatus includes a decision feedback equalizer configured to receive a parallel signal generated based on a first clock. The decision feedback equalizer includes a first equalization block configured to receive a first symbol of a first set of parallel symbols provided by the parallel signal during a first clock cycle of the first clock. A decision feedback equalization is performed by the first equalization block to the first symbol to provide a first decision to a second…

Diagnostic coverage of registers by software

Granted: August 15, 2017
Patent Number: 9734032
A programmable IC is disclosed that includes a programmable logic sub-system, a processing sub-system, and a safety sub-system. The programmable logic sub-system is configured to operate a hardware portion of the user design. The processing sub-system configured to execute a software portion of the user design. The safety sub-system is configured to perform a set of operations to detect errors in the programmable IC. The first set of operations writes to at least one of a set of…

Variable code rate solid-state drive

Granted: August 8, 2017
Patent Number: 9727416
An apparatus, as well as a method therefor, relates generally to managing reliability of a solid state storage. In such an apparatus, there is a memory controller for providing a code rate. An encoder is for receiving input data and the code rate for providing encoded data. The solid-state storage is for receiving and storing the encoded data. A decoder is for accessing the encoded data stored in the solid-state storage and for receiving the code rate for providing decoded data of the…

Multimode multiplexer-based circuit

Granted: August 8, 2017
Patent Number: 9729153
A device includes a multiplexer circuit with a plurality of input circuits. Each input circuit is connected to a respective input node and a shared output node. The input circuits are configured to pass, in response to a respective control signal, a signal between the respective input and shared output node. An output circuit is configured to store data from the shared output node in a latch mode and to act as a buffer in a pass-through mode. A control circuit is configured to switch, in…

Encoding scheme for processing pulse-amplitude modulated (PAM) signals

Granted: August 8, 2017
Patent Number: 9729170
An integrated circuit (IC) includes a serial-to-parallel converter configured to receive a serial input signal to provide one or more parallel output signals. The serial input signal is an M-level Pulse-Amplitude Modulated (PAM) signal, wherein M is a positive integer. The serial-to-parallel converter includes a data converter configured to receive the serial input signal and provide a data converter output signal. The data converter output signal represents information of the serial…

Bridging inter-bus communications

Granted: August 1, 2017
Patent Number: 9720868
Approaches for bridging communication between first and second buses are disclosed. Address translation information and associated security indicators are stored in a memory. Each access request from the first bus includes a first requester security indicator and a requested address. Each access request from the first bus and directed to the second bus is either rejected, or translated and communicated to the second bus, based on the requester security indicator and the security…

Processing system display controller interface to programmable logic

Granted: August 1, 2017
Patent Number: 9721528
In an example, a programmable integrated circuit (IC) includes programmable logic and a display controller. The display controller includes a first interface coupled to receive coded data, a renderer to generate display-agnostic data from the coded data, a transmitter to generate display data from the display-agnostic data in accordance with a first protocol, a second interface coupled to provide the display data as output, and a third interface coupled to provide the display-agnostic…

Circuit for and method of implementing a write operation of a memory

Granted: August 1, 2017
Patent Number: 9721649
A circuit for implementing a write operation of a memory is described. The circuit comprises a data line buffer coupled to a data line and an inverted data line for writing data; a plurality of memory elements, each memory element having a first node coupled to the data line and a second node coupled to the inverted data line; and a write assist circuit having a first node coupled to data line and a second node coupled to the inverted data line, wherein the write assist circuit comprises…

Current-mode logic circuit having a wide operating range

Granted: August 1, 2017
Patent Number: 9722604
In one example, a current-mode logic (CML) circuit includes a differential transistor pair having a differential input port configured to receive a differential input voltage, a bias port configured for coupling to a current source, and a differential output port. The CML circuit further includes a load circuit coupled to the differential output port. The load circuit includes an active inductive load, a cross-coupled transistor pair, and a switch coupled between the cross-coupled…

Circuit arrangement for and a method of enabling a partial reconfiguration of a circuit implemented in an integrated circuit device

Granted: August 1, 2017
Patent Number: 9722613
A circuit arrangement for enabling a partial reconfiguration of a circuit implemented in an integrated circuit device is described. The circuit arrangement comprises a plurality of circuit blocks, wherein each circuit block is configurable to implement a predetermined function and comprises a control circuit configured to receive a global enable signal and a plurality of global reconfiguration signals; and a routing network coupled to the plurality of circuit blocks for routing the…

Delivering circuit designs for programmable integrated circuits

Granted: July 18, 2017
Patent Number: 9710582
Implementing a circuit design may include, responsive to a user input selecting a design, executing an implementation script of the design using the processor. Executing the implementation script may generate instructions for generating a circuit design from the design. Responsive to the instructions and using the processor, cores of the design may be automatically instantiated and connected.

Performance of circuitry generated using high-level synthesis

Granted: July 18, 2017
Patent Number: 9710584
Implementing circuitry from an application may include partitioning an array of the application into a plurality of virtual blocks according to a streaming dimension of the array and determining that a first function and a second function of the application that access the array have same access patterns for the virtual blocks of the array. A first-in-first out (FIFO) memory may be included in a circuit design implementing the application. The FIFO memory couples a first circuit block…

Circuits for and methods of controlling the operation of a hybrid memory system

Granted: July 18, 2017
Patent Number: 9711194
A circuit for controlling the operation of a memory system having different types of memory is described. The circuit comprises a first memory having a first type of memory element and having a first access time; a second memory having a second type of memory element and having a second access time, wherein the second type of memory element is different than the first type of memory element; a memory control circuit enabling access to the first memory and the second memory; a delay…

Digitally-controlled impedance control for dynamically generating drive strength for a transmitter

Granted: July 18, 2017
Patent Number: 9712257
An apparatus, and method therefor, relates generally to a transmitter. In such an apparatus, a decoder is configured to receive a data input and control signals and to generate state signals responsive to a control signal of the control signals and data polarity the data input. Select circuitry is configured to receive coded signals to replace the data input with a pull-up code and a pull-down code of the coded signals responsive to the state signals and the control signals for…

System level simulation wrapper for hybrid simulation

Granted: July 11, 2017
Patent Number: 9703900
A system level simulation wrapper includes a plurality of port interfaces configured to provide pin accurate and bus cycle accurate communication. The system also includes a switch coupled to the plurality of port interfaces. The switch is selectively configured to communicate with a Cycle Accurate hardware description language (HDL) model of an intellectual property (IP) block or a system level model of the IP block.

Programmable reference voltage regulator

Granted: July 4, 2017
Patent Number: 9696747
An example a voltage regulator includes: a bias circuit coupled to an output node; a first operational amplifier having a first input coupled to the output node, a second input coupled to a reference voltage node, and an output coupled to a first node; a second operational amplifier having a first input coupled to the output node, a second input coupled to the reference voltage node, and an output coupled to a second node; an output transistor coupled between the output node and a ground…

Sub-system power management control

Granted: July 4, 2017
Patent Number: 9696789
An apparatus is disclosed that includes a processing sub-system having a plurality of processor circuits and an interrupt control circuit. The interrupt control circuit is configured to, in response to a peripheral interrupt, initiate performance of a task indicated by the peripheral interrupt by at least one of the plurality of processor circuits. The processing sub-system is configured to generate a power-down control signal in response to suspension of the plurality of processor…

System and method for integrated circuit handling and tracking

Granted: July 4, 2017
Patent Number: 9697402
An example method of tracking information for integrated circuits (ICs) that are handled by a plurality of tools during manufacture includes: marking each of IC with a barcode after the ICs have been packaged; performing, at a first tool of the plurality of tools, one or more electrical tests of the ICs and storing electrical characteristics of each IC in association with the barcode of each IC in a database; querying the database with a specification to obtain a set of barcodes for…

Low-power phase interpolator with wide-band operation

Granted: July 4, 2017
Patent Number: 9698970
An example clock delivery system includes a phase-locked loop (PLL) configured to generate a plurality of input clocks, a phase interpolator configured to receive the plurality of input clocks and generate a plurality of output clocks, and a clock data recovery (CDR) circuit configured to receive the plurality of output clocks. The phase interpolator includes a decoder having a plurality of inputs configured to receive binary codes and a respective plurality of outputs configured to…