Xilinx Patent Grants

Monolithic integrated circuit die having modular die regions stitched together

Granted: January 17, 2017
Patent Number: 9547034
An apparatus for a monolithic integrated circuit die is disclosed. In this apparatus, the monolithic integrated circuit die has a plurality of modular die regions. The modular die regions respectively have a plurality of power distribution networks for independently powering each of the modular die regions. Each adjacent pair of the modular die regions is stitched together with a respective plurality of metal lines.

High voltage RC-clamp for electrostatic discharge (ESD) protection

Granted: January 17, 2017
Patent Number: 9548738
In accordance with some embodiments, an electrostatic discharge (ESD) protection circuit for high-voltage power rails includes an RC-triggered clamp having an RC-circuit having a resistor coupled between a first node and a second node, and a capacitor coupled between the second node and a third node. The RC-triggered clamp also has a transistor with a first source/drain, a gate, and a second source/drain, wherein the first source/drain is coupled to the first node, and the second…

Determination of configuration values and configuration of frequency multiplier and frequency divider circuitry

Granted: January 10, 2017
Patent Number: 9543934
In an approach for determining multiplier values and divisor values for programming frequency multiplier and divider circuits in a clock network, respective requested frequency values and respective tolerance levels relative to the requested frequency values for a plurality of clocked circuit blocks are used. Multiple solution sets are generated, with each solution set including a multiplier value and an associated set of values of divisors, such that resulting actual frequencies satisfy…

Leaf-level generation of phase-shifted clocks using programmable clock delays

Granted: January 3, 2017
Patent Number: 9537491
Methods and apparatus for generating multiple phase-shifted clock signals from a base clock signal using programmable delays at the leaf level in a clock distribution network are described. One example method for generating and distributing multiple phase-shifted clock signals in a programmable integrated circuit (IC) generally includes generating a base clock signal, routing the base clock signal through a clock distribution network in the programmable IC to a leaf node, and applying…

Error protection for bus interconnect circuits

Granted: December 27, 2016
Patent Number: 9529686
In an approach for detecting faults on a bus interconnect that connects a bus master circuit to bus slave circuits, application program code and fault detection program code are concurrently executed by a bus master circuit. The application program code initiates first bus transactions to the bus slave circuits, and the fault detection program code initiates second bus transactions to the bus slave circuits for detection of faults in data channels of the bus interconnect. An error code…

Performance estimation using configurable hardware emulation

Granted: December 27, 2016
Patent Number: 9529946
An integrated circuit can include a processor operable to execute program code and an Intellectual Property (IP) modeling block. The IP modeling block can include a first port through which the IP modeling block receives first modeling data and a second port coupled to the processor through which the first IP modeling block communicates with the processor during emulation. The first IP modeling block also can include a power emulation circuit. The power emulation circuit is configured to…

Multithreaded scheduling for placement of circuit designs using connectivity and utilization dependencies

Granted: December 27, 2016
Patent Number: 9529957
Placing a circuit design may include partitioning circuit elements of the circuit design into circuit element sets and grouping bins of an integrated circuit into bin sets. The bins include circuit elements of the circuit design from an initial placement. Placing a circuit design also may include determining a dependency connectivity metric for the circuit elements and, using a processor, selectively relocating circuit elements concurrently, for a plurality of iterations, using a cost…

Protection of designs for electronic systems

Granted: December 27, 2016
Patent Number: 9530022
In one approach for protecting a design, a plurality of implementations of the design are generated. Each implementation includes an identification function. One of the implementations is selected as a current implementation, and the current implementation is installed on one or more electronic systems. For each electronic system, a method determines whether or not the current implementation is an authorized version on the electronic system from an output value of the identification…

Configurable latch circuit

Granted: December 27, 2016
Patent Number: 9531351
In an example implementation, a circuit includes first and second latch circuits. A circuit coupled to the first and second latch circuits is configured to provide a first clock signal to the clock input node of the second latch circuit and provide a second clock signal that is an inversion of the first clock signal to the clock input node of the first latch circuit. The circuit includes a first multiplexer having a first input node coupled to a data output node of the first latch…

Capacitor structure in an integrated circuit

Granted: December 20, 2016
Patent Number: 9524964
In an example, a capacitor in an integrated circuit (IC), includes: a first finger capacitor formed in at least one layer of the IC having a first bus and a second bus; a second finger capacitor formed in the at least one layer of the IC having a first bus and a second bus, where a longitudinal edge of the second bus of the second finger capacitor is adjacent a longitudinal edge of the first bus of the first finger capacitor and separated by a dielectric gap; and a first metal segment…

Power distribution network IP block

Granted: December 20, 2016
Patent Number: 9525423
A device comprises a semiconductor substrate, a programmable logic device on the semiconductor substrate, a power distribution network comprising at least one voltage regulator on the semiconductor substrate, and a power management bus for communication between the at least one voltage regulator and the programmable logic device. The programmable logic device comprises a processing module configured to perform a diagnostic analysis of the power distribution network.

Adaptive multiple-input multiple-output (MIMO) data detection and precoding

Granted: December 20, 2016
Patent Number: 9525470
A system includes a memory and an integrated circuit coupled to the memory. The integrated circuit is configured to communicate data in a channel characterized as a space having at least a frequency dimension. Anchor locations within the space correspond to respective regions of the space. The integrated circuit is further configured to determine a first inverse of a first matrix that corresponds to a first channel matrix for a first anchor location of the anchor locations. The first…

Method of and device for processing data using a pipeline of processing blocks

Granted: December 13, 2016
Patent Number: 9519486
A method of processing data in an integrated circuit is described. The method comprises establishing a pipeline of processing blocks, wherein each processing block has a different function; coupling a data packet having data and meta-data to an input of the pipeline of processing blocks; and processing the data of the data packet using predetermined processing blocks based upon the meta-data. A device for processing data in an integrated circuit is also described.

Optical communication circuits

Granted: December 13, 2016
Patent Number: 9520949
Various apparatuses, circuits, systems, and methods for optical communication are disclosed. In some implementations an optical transmitter includes an optical data port configured to engage an optical fiber. The optical transmitter also includes a plurality of lasers coupled to the optical data port and configured and arranged to transmit respective optical signals over the optical fiber via the optical data port when selected. A control circuit of the optical transmitter is configured…

Methods for flip chip stacking

Granted: November 29, 2016
Patent Number: 9508563
A method for flip chip stacking includes forming a cavity wafer comprising a plurality of cavities and a pair of corner guides, placing a through-silicon-via (TSV) interposer with solder bumps coupled to a surface of the TSV interposer on the cavity wafer, such that the solder bumps are situated in the plurality of cavities and the TSV interposer is situated between the pair of corner guides, placing an integrated circuit (IC) die on another surface of the TSV interposer, such that the…

Interconnect multiplexers and methods of reducing contention currents in an interconnect multiplexer

Granted: November 29, 2016
Patent Number: 9509307
An interconnect multiplexer comprises a plurality of CMOS pass gates of a first multiplexer stage coupled to receive data to be output by the interconnect multiplexer; an output inverter coupled to the outputs of the plurality of CMOS pass gates, wherein an output of the output inverter is an output of the interconnect multiplexer; and a plurality of memory elements coupled to the plurality of CMOS pass gates; wherein inputs to the plurality of CMOS pass gates are pulled to a common…

Latency control in a transmitter/receiver buffer

Granted: November 29, 2016
Patent Number: 9509640
In a method for buffering, a buffer buffers data responsive to read and write clock signals. A flag signal from the buffer is for a fill level thereof. The flag signal is toggled responsive to the data buffered being either above or below a set point for the fill level. A phase of the write clock signal is adjusted to a phase of the read clock signal responsive to the toggling of the flag signal. The write clock signal is used to control latency of the buffer. The adjusting of the phase…

Virtualization of programmable integrated circuits

Granted: November 22, 2016
Patent Number: 9503093
A programmable IC includes a plurality of programmable resources, a plurality of shareable logic circuits coupled to the plurality of programmable resources, and a virtualization circuit. The plurality of programmable resources includes programmable logic circuits and programmable routing resources. The virtualization circuit is configured to manage sharing of the plurality of shareable logic circuits between a plurality of user designs implemented in the plurality of programmable…

Circuit for and method of implementing a time-interleaved analog-to-digital converter

Granted: November 22, 2016
Patent Number: 9503115
A circuit for implementing a time-interleaved analog-to-digital converter is described. The circuit comprises a sampling clock generator configured to receive a reference clock signal having a first frequency. The sampling clock generator has a first stage sampling clock generator configured to generate a first plurality of clock signals based upon the reference clock signal and having a second frequency, and a second stage sampling clock generator configured to generate, for each clock…

Noise-shaping crest factor reduction with polyphase transforming

Granted: November 22, 2016
Patent Number: 9503301
Apparatus, system and method relates generally to data communication with noise-shaping crest factor reduction using polyphase transformation. In such a method, a composite signal is received by a delay and a waveform generator. The waveform generator is for noise-shaping crest factor reduction using polyphase transformation. The composite signal is delayed by the delay to provide a delayed composite signal. A waveform is generated by the waveform generator from the composite signal. The…