Xilinx Patent Grants

Delivering circuit designs for programmable integrated circuits

Granted: July 18, 2017
Patent Number: 9710582
Implementing a circuit design may include, responsive to a user input selecting a design, executing an implementation script of the design using the processor. Executing the implementation script may generate instructions for generating a circuit design from the design. Responsive to the instructions and using the processor, cores of the design may be automatically instantiated and connected.

Performance of circuitry generated using high-level synthesis

Granted: July 18, 2017
Patent Number: 9710584
Implementing circuitry from an application may include partitioning an array of the application into a plurality of virtual blocks according to a streaming dimension of the array and determining that a first function and a second function of the application that access the array have same access patterns for the virtual blocks of the array. A first-in-first out (FIFO) memory may be included in a circuit design implementing the application. The FIFO memory couples a first circuit block…

Circuits for and methods of controlling the operation of a hybrid memory system

Granted: July 18, 2017
Patent Number: 9711194
A circuit for controlling the operation of a memory system having different types of memory is described. The circuit comprises a first memory having a first type of memory element and having a first access time; a second memory having a second type of memory element and having a second access time, wherein the second type of memory element is different than the first type of memory element; a memory control circuit enabling access to the first memory and the second memory; a delay…

Digitally-controlled impedance control for dynamically generating drive strength for a transmitter

Granted: July 18, 2017
Patent Number: 9712257
An apparatus, and method therefor, relates generally to a transmitter. In such an apparatus, a decoder is configured to receive a data input and control signals and to generate state signals responsive to a control signal of the control signals and data polarity the data input. Select circuitry is configured to receive coded signals to replace the data input with a pull-up code and a pull-down code of the coded signals responsive to the state signals and the control signals for…

System level simulation wrapper for hybrid simulation

Granted: July 11, 2017
Patent Number: 9703900
A system level simulation wrapper includes a plurality of port interfaces configured to provide pin accurate and bus cycle accurate communication. The system also includes a switch coupled to the plurality of port interfaces. The switch is selectively configured to communicate with a Cycle Accurate hardware description language (HDL) model of an intellectual property (IP) block or a system level model of the IP block.

Programmable reference voltage regulator

Granted: July 4, 2017
Patent Number: 9696747
An example a voltage regulator includes: a bias circuit coupled to an output node; a first operational amplifier having a first input coupled to the output node, a second input coupled to a reference voltage node, and an output coupled to a first node; a second operational amplifier having a first input coupled to the output node, a second input coupled to the reference voltage node, and an output coupled to a second node; an output transistor coupled between the output node and a ground…

Sub-system power management control

Granted: July 4, 2017
Patent Number: 9696789
An apparatus is disclosed that includes a processing sub-system having a plurality of processor circuits and an interrupt control circuit. The interrupt control circuit is configured to, in response to a peripheral interrupt, initiate performance of a task indicated by the peripheral interrupt by at least one of the plurality of processor circuits. The processing sub-system is configured to generate a power-down control signal in response to suspension of the plurality of processor…

System and method for integrated circuit handling and tracking

Granted: July 4, 2017
Patent Number: 9697402
An example method of tracking information for integrated circuits (ICs) that are handled by a plurality of tools during manufacture includes: marking each of IC with a barcode after the ICs have been packaged; performing, at a first tool of the plurality of tools, one or more electrical tests of the ICs and storing electrical characteristics of each IC in association with the barcode of each IC in a database; querying the database with a specification to obtain a set of barcodes for…

Low-power phase interpolator with wide-band operation

Granted: July 4, 2017
Patent Number: 9698970
An example clock delivery system includes a phase-locked loop (PLL) configured to generate a plurality of input clocks, a phase interpolator configured to receive the plurality of input clocks and generate a plurality of output clocks, and a clock data recovery (CDR) circuit configured to receive the plurality of output clocks. The phase interpolator includes a decoder having a plurality of inputs configured to receive binary codes and a respective plurality of outputs configured to…

Methods and circuits for debugging circuit designs

Granted: June 13, 2017
Patent Number: 9678150
Various example implementations are directed to circuits and methods for debugging circuit designs. According to an example implementation, waveform data is captured, for a set of signals produced by a circuit design during operation. Data structures are generated for the set of signals and waveform data for the signals is stored in the data structures. Communication channels associated with the set of signals are identified. Waveform data stored in the data structures is analyzed to…

Constraint handling for parameterizable hardware description language

Granted: June 13, 2017
Patent Number: 9679092
Constraint handling for a circuit design may include determining, using a processor, instances of parameterizable modules of a circuit design associated with constraints based upon a predefined hardware description language attribute within the instances, extracting, using the processor, parameter values from the instances of the parameterizable modules, and generating, using the processor, static constraint files for the instances of the parameterizable modules using the extracted…

System and method to reduce footprint and improve yield of fabric muxes in programmable logic devices

Granted: June 13, 2017
Patent Number: 9680474
An interconnect element includes: a selection circuit for receiving input signals and having a selection output; a half-latch circuit having an input coupled to the selection output, wherein the half latch circuit comprises a pull-up device; and a common bias circuit coupled to the pull-up device, wherein the common bias circuit is configured to supply a tunable bias voltage to the pull-up device.

Threshold detection with digital correction in analog to digital converters

Granted: June 13, 2017
Patent Number: 9680492
An analog to digital converter (ADC) includes a comparator and a plurality of capacitor pairs coupled between first and second inputs the comparator, where each one of the capacitor pairs corresponds to one of a plurality of cycles used by the ADC to generate a digital value representing a sampled analog voltage. The ADC also includes a voltage detection circuit and a state machine that is configured to, upon determining during a first cycle that the sampled voltage across the first and…

Interconnect circuitry fault detection

Granted: June 6, 2017
Patent Number: 9672094
Fault detection for an interconnect bus includes performing safety register validation including validating correct operation of a safety register in a slave circuit. The safety register is reserved for validation operations. Write bus validation is performed where, over an address range of the slave circuit, received write addresses within the address range are stored in the safety register of the slave circuit and read back by a master circuit for validation. Read bus validation is…

Circuits for and methods of generating a modulated signal in a transmitter

Granted: June 6, 2017
Patent Number: 9674015
A circuit for generating a modulated signal in a transmitter of an integrated circuit is disclosed. The circuit comprises a transmitter driver circuit having a first current path for receiving a first input signal of a pair of differential input signals and a second current path for receiving a second input signal of the pair of differential input signals, the transmitter driver circuit comprising a tail current path coupled to each of the first current path and the second current path;…

Efficient mapping of table pipelines for software-defined networking (SDN) data plane

Granted: June 6, 2017
Patent Number: 9674081
Methods and apparatus for using dynamic programming to determine the most efficient mapping of a pipeline of virtual flow tables (VFTs) onto a pipeline of physical flow tables (PFTs) in the data plane of a software-defined networking (SDN) device are described. One example method of determining a configuration for an SDN device generally includes receiving a representation of a series of one or more VFTs, each of the VFTs having one or more properties; receiving a representation of a…

Mechanism for inter-processor interrupts in a heterogeneous multiprocessor system

Granted: May 30, 2017
Patent Number: 9665509
Apparatus and methods for handling inter-processor interrupts (IPIs) in a heterogeneous multiprocessor system are provided. The scalable IPI mechanism provided herein entails minimal logic and can be used for heterogeneous inter-processor communication, such as between application processors, real-time processors, and FPGA accelerators. This mechanism is also low cost, in terms of both logic area and programmable complexity. One example system generally includes a first processor, a…

Emulating power gating for a circuit design using a programmable integrated circuit

Granted: May 30, 2017
Patent Number: 9665671
Emulating power gating includes identifying an isolation circuit having a first input coupled to an output of a first power domain, a second input coupled to an isolation signal, and an output coupled to an input of a second power domain; removing a power gate circuit configured to selectively decouple the first power domain from a power supply responsive to a power gate signal; and decoupling the first input of the isolation circuit from the output of the first power domain. A power…

Designing a system for a programmable system-on-chip using performance characterization techniques

Granted: May 30, 2017
Patent Number: 9665683
An example method of implementing a system design for a programmable system-on-chip (SOC) having a processing system and programmable logic includes receiving a description of performance objectives for the system design. The method further includes accessing a characterization database that relates parameter settings of the processing system to performance under different traffic profiles as generated by an emulation system comprising the processing system and one or more circuit blocks…

Secure configuration readback for programmable logic devices

Granted: May 30, 2017
Patent Number: 9666248
A programmable integrated circuit, includes an external port, a configuration memory, a hardened write path between the external port and the configuration memory and a soft read path between the configuration memory and the external port, wherein configuration data stored in the configuration memory is only read through the soft read path.