Universal interposer for a semiconductor package
Granted: February 13, 2024
Patent Number:
11901300
A universal interposer for an integrated circuit (IC) device has a body having a first surface and a second surface opposite the first surface. A first region is formed on a first side of the body along a first edge. The first region has first slots, each having an identical first bond pad layout. A second region is formed on the first side along a second edge, opposite the first edge. The second region has second slots having an identical second bond pad layout. A third region having…
Interwafer connection structure for coupling wafers in a wafer stack
Granted: February 13, 2024
Patent Number:
11901338
An integrated circuit (IC) device is disclosed which includes at least a first hybrid bond interface layer disposed between adjacent wafers of a wafer stack. Routing within the hybrid bond interface layer allows test pads exposed on a top wafer of the wafer stack to electrically couple test keys within the wafer stack. By utilizing the routing within the hybrid bond interface layer to index electrical connections between adjacent wafers, IC dies stacked on the wafers may be fabricated…
Universal interposer for a semiconductor package
Granted: February 13, 2024
Patent Number:
11901300
A universal interposer for an integrated circuit (IC) device has a body having a first surface and a second surface opposite the first surface. A first region is formed on a first side of the body along a first edge. The first region has first slots, each having an identical first bond pad layout. A second region is formed on the first side along a second edge, opposite the first edge. The second region has second slots having an identical second bond pad layout. A third region having…
Ultra-high-speed PAM-N CMOS inverter serial link
Granted: February 6, 2024
Patent Number:
11894959
Methods, systems, and apparatus described herein make a multi-level PAM signal (PAM-N signal) at a transmitter using CMOS-based components. By forming the PAM-N signal at the transmitter, receivers do not have to recombine and/or realign multiple signals and only employs a single transmission line channel (or two transmission line channels in differential implementations) to convey the data stream to the receiver from the transmitter.
Multi-use chip-to-chip interface
Granted: February 6, 2024
Patent Number:
11892966
Systems, methods, and apparatuses are described that enable IC architectures to enable a single anchor to connect to and accept a variety of chiplets at any port by way of a programming model that enables the anchor or chiplet to dynamically adapt to configurations, requirements, or aspects of any coupled component and provide an interface for the coupled components.
Cached system for managing state vectors
Granted: January 30, 2024
Patent Number:
11886344
A cache system includes a computational cache and a computational cache miss-handler. The computational cache is configured to cache state vectors and perform read-modify-write (RMW) operations on the cached state vectors responsive to received RMW commands. The computational cache miss-handler is configured to perform RMW operations on state vectors stored in a memory responsive to cache misses in the computational cache. The memory is external to the cache system.
Time-division multiplexing (TDM) in integrated circuits for routability and runtime enhancement
Granted: January 30, 2024
Patent Number:
11888693
Implementing a circuit design using time-division multiplexing (TDM) can include determining a net signature for each of a plurality of nets of a circuit design. For each net, the net signature specifies location information for a driver and one or more loads of the net. The plurality of nets having a same net signature can be grouped according to distance between drivers of the respective nets. One or more subgroups can be generated based on a TDM ratio for each group. For one or more…
Method and apparatus for memory management in a video processing system
Granted: January 30, 2024
Patent Number:
11887558
An integrated circuit (IC) includes a video buffer memory and display driver circuitry. The video buffer memory includes a buffer memory map. The video buffer memory stores one or more raster lines of video data organized as tiled lines. Each of the tiled lines including two quartiles. The display driver circuitry is coupled to the video buffer memory. The display driver circuitry writes data associated with a portion of a first data line to a first one of the two quartiles of a first…
Acceleration-ready program development and deployment for computer systems and hardware acceleration
Granted: January 30, 2024
Patent Number:
11886854
Acceleration-ready program development includes providing a software library having a plurality of functions having compute identifiers. The software library is associated with a hardware library including one or more hardware accelerated functions. The hardware accelerated functions are associated with the compute identifiers. Each hardware accelerated function is a functional equivalent of a function of the software library having the same compute identifier. A hybrid executor layer is…
Block design containers for circuit design
Granted: January 30, 2024
Patent Number:
11886789
Circuit design development using block design containers can include opening, within a development environment generated by an Electronic Design Automation (EDA) system, a top-level block design specifying a circuit design and inserting, within the top-level block design using the EDA system, a block design container. The block design container specifies a source block design used as a sub-design within the top-level block design.
Receiver circuitry having a transistor pair for input voltage clipping
Granted: January 23, 2024
Patent Number:
11881884
Receiver circuitry for an input/output device includes first stage circuitry and second stage. The first stage circuitry has a first input to receive an input signal, voltage adjustment circuitry, and differential amplifier circuitry. The first stage circuitry is coupled to the first input and has a transistor pair to receive the input signal, and adjust a voltage value of the input signal to generate an adjusted signal. The differential amplifier circuitry receives the adjusted signal…
TCP processing for devices
Granted: January 16, 2024
Patent Number:
11876880
A data processing system is provided. A host processing device supports a host transport engine operable to establish a first transport stream over a network with a remote peer. Device hardware comprises a device transport engine. The device transport engine is configured to monitor the first transport stream to determine a state of the first transport stream and in response to an indication from the host processing device perform transport processing of the first transport stream.
DPLL timing normalization
Granted: January 16, 2024
Patent Number:
11876523
Embodiments herein describe normalizing an output of a TDC in a DPLL to a resolution of the TDC. A DTC can delay a reference clock which is then input into the TDC. The TDC outputs a digital code indicating a time difference between the delayed reference clock output by the DTC and a clock generated by a DCO in the DPLL. This digital code is normalized to a resolution of the TDC and the result is filtered by a DLF.
Distributed parallel processing routing
Granted: January 16, 2024
Patent Number:
11875100
Examples described herein provide a non-transitory computer-readable medium storing instructions, which when executed on one or more processors, cause the one or more processors to perform operations. The operations include generating a plurality of child processes according to a number of a plurality of partitions in an integrated circuit (IC) design for an IC die, each of the plurality of child processes corresponding to and assigned to a respective one of the plurality of partitions.…
Flash memory emulation
Granted: January 16, 2024
Patent Number:
11874768
Disclosed approaches for emulating flash memory include storage circuits having respective address decoders. An input-output circuit has pins compatible with a flash memory device and is configured to input flash commands and output response signals via pins. An emulator circuit is configured to translate each flash command into one or more storage-circuit commands compatible with one storage circuit of the storage circuits, and to generate response signals compatible with the flash…
Clock tree routing in a chip stack
Granted: January 9, 2024
Patent Number:
11868174
Examples described herein generally relate to clock tree routing in a chip stack. In an example, a multi-chip device includes a chip stack. The chip stack includes chips. The chip stack includes a clock tree. In-chip routing of the clock tree is contained within one logical chip of the chip stack. The chip stack includes leaf nodes disposed in respective chips. Each leaf node of the leaf nodes is electrically connected to the clock tree through a respective leaf-level connection bridge.…
Integrated circuit chip testing interface with reduced signal wires
Granted: January 2, 2024
Patent Number:
11860228
An integrated circuit (IC) chip device includes testing interface circuity and testing circuitry to test the operation of the IC chips of the IC chip device. The IC chip device includes a first IC chip that comprises first testing circuitry. The first testing circuitry receives a mode select signal, a clock signal, and encoded signals, and comprises finite state machine (FSM) circuitry, decoder circuitry, and control circuitry. The FSM circuitry determines an instruction based on the…
Flow control between non-volatile memory storage and remote hosts over a fabric
Granted: January 2, 2024
Patent Number:
11861326
An example method of flow control between remote hosts and a target system over a front-end fabric, the target system including a nonvolatile memory (NVM) subsystem coupled to a back end fabric having a different transport than the front-end fabric is described. The method includes receiving commands from the remote hosts at a controller in the target system for the NVM subsystem. The method further includes storing the commands in a first-in-first-out (FIFO) shared among the remote…
High-throughput regular expression processing with capture using an integrated circuit
Granted: January 2, 2024
Patent Number:
11861171
A system includes a first multi-port RAM storing an instruction table. The instruction table specifies a regular expression for application to a data stream and a second multi-port RAM configured to store a capture table having capture entries decodable for tracking position information for a sequence of characters matching a capture sub-expression of the regular expression. The system includes a regular expression engine processing the data stream to determine match states by tracking…
Extensible device hosted root of trust architecture for integrated circuits
Granted: January 2, 2024
Patent Number:
11861010
An integrated circuit can include a communication endpoint configured to maintain a communication link with a host computer, a queue configured to receive a plurality of host commands from the host computer via the communication link, and a processor configured to execute a device runtime. The processor, responsive to executing the device runtime, is configured to perform validation of the host commands read from the queue and selectively execute the host commands based on a result of…
