Integrated circuit chip testing interface with reduced signal wires
Granted: January 2, 2024
Patent Number:
11860228
An integrated circuit (IC) chip device includes testing interface circuity and testing circuitry to test the operation of the IC chips of the IC chip device. The IC chip device includes a first IC chip that comprises first testing circuitry. The first testing circuitry receives a mode select signal, a clock signal, and encoded signals, and comprises finite state machine (FSM) circuitry, decoder circuitry, and control circuitry. The FSM circuitry determines an instruction based on the…
Calibrating a multiplexer of an integrated circuit
Granted: December 26, 2023
Patent Number:
11855652
A multiplexer (MUX) calibration system includes main MUX circuitry, first replica MUX circuitry, digital-to-analog (DAC) circuitry, detection circuitry, and control circuitry. The main MUX circuitry receives clock signals and outputs a first data signal based on the clock signals. The first replica MUX circuitry receives the clock signals and outputs a second data signal based on the clock signals. The DAC circuitry generates an offset voltage. The detection circuitry receives the second…
Communicating between data processing engines using shared memory
Granted: December 26, 2023
Patent Number:
11853235
Examples herein describe techniques for transferring data between data processing engines in an array using shared memory. In one embodiment, certain engines in the array have connections to the memory in neighboring engines. For example, each engine may have its own assigned memory module which can be accessed directly (e.g., without using a streaming or memory mapped interconnect). In addition, the surrounding engines (referred to herein as the neighboring engines) may also include…
Multiple partitions in a data processing array
Granted: December 19, 2023
Patent Number:
11848670
An apparatus includes a data processing array having a plurality of array tiles. Each array tile can include a random-access memory (RAM) having a local memory interface accessible by circuitry within the array tile and an adjacent memory interface accessible by circuitry disposed within an adjacent array tile. Each adjacent memory interface of each array tile can include isolation logic that is programmable to allow the circuitry disposed within the adjacent array tile to access the RAM…
System and method for capturing data to provide to a data analyser
Granted: December 19, 2023
Patent Number:
11847108
A system has data capture devices collecting data from different points in a network. The captured data is written to a data store and is directed to an output. The data from the different data capture devices can be delivered to a data analytics device. As long as the data analytics device is able to keep pace with the data that is directed to the output, that data is used by the analytics device. If the analytics device is not able to keep pace, the data written to the data store is…
Circuit architecture for determining threshold ranges and values of a dataset
Granted: December 12, 2023
Patent Number:
11842168
An electronic system includes a mapping circuit configured to receive input samples of a dataset within a defined range of values. The mapping circuit is configured to perform comparisons that compare each input sample to each of a plurality of comparison values selected from the defined range of values. For each comparison, the mapping circuit generates an indication value specifying whether the input sample used in the comparison is greater than or equal to the comparison value used in…
Early detection of sequential access violations for high level synthesis
Granted: December 5, 2023
Patent Number:
11836426
Detecting sequential access violations for high-level synthesis (HLS) includes performing a simulation, using computer hardware, of an application for HLS. During the simulation, accesses of the application to elements of an array of the application are detected. During the simulation, determinations of whether the accesses occur in a sequential order are made. An indication of whether the access occur in sequential order is generated.
Synthesis flow for data processing engine array applications relying on hardware library packages
Granted: November 28, 2023
Patent Number:
11829733
Implementing an application for a data processing engine (DPE) array can include detecting, using computer hardware, a component of a hardware library package instantiated by an application. The application is specified in source code and is configured to execute on a DPE array. An instance of the component is extracted from the application. The extracted instance specifies values of parameters for the instance of the component. The instance can be partitioned by generating program code…
Localized NoC switching interconnect for high bandwidth interfaces
Granted: November 28, 2023
Patent Number:
11832035
Embodiments herein describe an integrated circuit that includes a NoC with at least two levels of switching: a sparse network and a non-blocking network. In one embodiment, the non-blocking network is a localized interconnect that provides an interface between the sparse network in the NoC and a memory system that requires additional bandwidth such as HBM2/3 or DDR5. Hardware elements connected to the NoC that do not need the additional benefits provided by the non-blocking network can…
Streaming architecture for packet parsing
Granted: November 28, 2023
Patent Number:
11831743
Apparatus and associated methods relate to packet header field extraction as defined by a high level language and implemented in a minimum number of hardware streaming parsing stages to speculatively extract header fields from among multiple possible header sequences. In an illustrative example, the number of stages may be determined from the longest possible header sequence in any received packet. For each possible header sequence, one or more headers may be assigned to each stage, for…
Network interface device
Granted: November 21, 2023
Patent Number:
11824830
A network interface device having a hardware module comprising a plurality of processing units. Each of the plurality of processing units is associated with its own at least one predefined operation. At a compile time, the hardware module is configured by arranging at least some of the plurality of processing units to perform their respective at least one operation with respect to a data packet in a certain order so as to perform a function with respect to that data packet. A compiler is…
Identifying alignment markers using partial correlators
Granted: November 21, 2023
Patent Number:
11824761
Methods and apparatus for detecting alignment markers in received data streams received via a plurality of data lanes are disclosed. Corresponding data streams may be received via respective data lanes in the plurality of data lanes, where each data stream includes alignment markers delineating data frames, and each alignment marker has a predefined bit pattern. For each respective data lane, a determination is made whether a specified portion of the received data stream has at least a…
Lossless compression using subnormal floating point values
Granted: November 21, 2023
Patent Number:
11824564
A disclosed compression method includes inputting a data set of floating point values from an input circuit to a compression circuit and detecting non-zero values and sequences of zero values in the data set. The compression circuit outputs, in response to detection of a non-zero value in the data set, the non-zero value to an output circuit. The compression circuit generates, in response to detection of a sequence of zero values in the data set, a subnormal floating point value having…
Pulse generator for injection locked oscillator
Granted: November 21, 2023
Patent Number:
11824548
A multiplication injection locked oscillator (MIILO) circuitry includes a ring injection locked oscillator (ILO) circuitry that outputs clock signals, a first switching circuitry and a second switching circuitry. The ring ILO circuitry includes a first path having first delay stages, and a second path having a second delay stages. The first switching circuitry is connected to the first path and a voltage supply node. The first switching circuitry receives a first control signal and a…
Transmit driver architecture with a jtag configuration mode, extended equalization range, and multiple power supply domains
Granted: November 21, 2023
Patent Number:
11824534
A transmit driver architecture with a test mode (e.g., a JTAG configuration mode), extended equalization range, and/or multiple power supply domains. One example transmit driver circuit generally includes one or more driver unit cells having a differential input node pair configured to receive an input data signal and having a differential output node pair configured to output an output data signal; a plurality of power switches coupled between the differential output node pair and one…
High-throughput regular expression processing with capture using an integrated circuit
Granted: November 14, 2023
Patent Number:
11816335
A system includes a first multi-port RAM storing an instruction table. The instruction table specifies a regular expression for application to a data stream and a second multi-port RAM configured to store a capture table having capture entries decodable for tracking position information for a sequence of characters matching a capture sub-expression of the regular expression. The system includes a regular expression engine processing the data stream to determine match states by tracking…
Breakout structure for an integrated circuit device
Granted: November 7, 2023
Patent Number:
11812544
Apparatus having at least one breakout structure are provided. In one example, an apparatus includes a dielectric layer, first and second contact pads, and first and second vias. The first and second contact pads are disposed on the dielectric layer. The first via is disposed through the dielectric layer and coupled to the first contact pad. The first via is offset from the first contact pad in a first direction. The second contact pad is immediately adjacent the first via. The second…
Programmed input/output mode
Granted: November 7, 2023
Patent Number:
11809367
A data processing system and method are provided. A host computing device comprises at least one processor. A network interface device is arranged to couple the host computing device to a network. The network interface device comprises a buffer for receiving data for transmission from the host computing device. The processor is configured to execute instructions to transfer the data for transmission to the buffer. The data processing system further comprises an indicator store configured…
Wafer-scale large programmable device
Granted: October 31, 2023
Patent Number:
11803681
The embodiments herein rely on cross reticle wires (also referred to as cross die wires) to provide communication channels between programmable dies already formed on a wafer. Using cross reticle wires to facilitate x-die communication can be three to four orders of magnitude faster than using general purpose I/O. With a wafer containing cross reticle wires, various device geometries can be generated at dicing time by cutting across different reticle boundaries. This allows up to full…
Predicting a performance metric based on features of a circuit design and explaining marginal contributions of the features to the prediction
Granted: October 17, 2023
Patent Number:
11790139
A design tool determines features of a circuit design and applies a first model to the features. The first model indicates a predicted value of a metric based on the plurality of features. The design tool applies an explanation model to the features, and the explanation model indicates levels of contributions by the features to the predicted value of the metric, respectively. The design tool selects a feature of the plurality of features based on the respective levels of contributions…
