Systems And Methods For Electronically Scanned Array Antennas
Granted: November 28, 2024
Application Number:
20240396579
An array of antennas includes transmitter and receiver circuits. The transmitter includes a digital-to-analog converter (DAC), splitter and filter circuits, and mixer circuits. The DAC circuit converts a digital signal into an analog signal. The splitter and filter circuits separate frequencies of the analog signal into split signals. The mixer circuits multiply frequencies from the split signals by different frequencies of carrier signals to generate modulated signals that are converted…
Circuits And Methods For Preventing Row Hammer Attacks To Memory Circuits
Granted: November 21, 2024
Application Number:
20240386102
An integrated circuit includes a control circuit configured to send a first command for accessing a row of a memory circuit to the memory circuit during a refresh cycle of the memory circuit. The integrated circuit also includes a first buffer circuit configured to store data accessed from the row of the memory circuit in response to the first command. The integrated circuit also includes a second buffer circuit configured to store an address for the data. The control circuit services a…
Output Driver Circuits And Methods With Hot-Socket Protection
Granted: October 24, 2024
Application Number:
20240356548
An integrated circuit includes an output driver circuit having first and second transistors coupled to an external pad of the integrated circuit and first and second multiplexer circuits. The first multiplexer circuit is configurable to cause the first transistor to be controlled by a first voltage during a data output mode of operation and to couple a first control input of the first transistor to the external pad during a hot-socket protection mode of operation. The second multiplexer…
Electronic Devices Having Oval Power Delivery Pads
Granted: September 26, 2024
Application Number:
20240321716
An electronic device includes conductive pads that are formed on a surface of the electronic device. Each of the conductive pads has an oval shape. The conductive pads are coupled to deliver at least one of a power supply voltage or a ground voltage between an external device and the electronic device.
Techniques For Transferring Heat From Electronic Devices Using Heatsinks
Granted: September 26, 2024
Application Number:
20240321670
An electronic device includes a first layer and a thermal heatsink that comprises a conductive region in a second layer of the electronic device. The thermal heatsink further comprises a first via that extends through the first layer. The first via is filled with conductive material that is coupled to the conductive region. The conductive material in the first via is coupled to an external terminal of the electronic device. The electronic device can also include a second via filled with…
Techniques For Testing Input And Output Buffer Circuits Using A Test Bus
Granted: September 26, 2024
Application Number:
20240319262
An integrated circuit includes first and second pads, a buffer circuit coupled to the first pad, a first pass gate circuit coupled to the first pad and to the buffer circuit, a second pass gate circuit coupled to the second pad, and a test bus coupled to the first pass gate circuit and the second pass gate circuit. The first pass gate circuit and the second pass gate circuit are configurable to couple the second pad to the buffer circuit through the test bus during a test of the buffer…
Techniques For Providing Supply Current To Dies In A System Using An Inductor
Granted: September 19, 2024
Application Number:
20240312905
An integrated circuit package includes first and second integrated circuit dies stacked vertically and coupled together, a connection device coupled to the first integrated circuit die, and a power delivery device coupled to the connection device. The power delivery device includes an inductor. The inductor generates supply current. The inductor is coupled to provide the supply current from the inductor to the first integrated circuit die through the connection device.
Frequency Multiplier, Signal Transmitter and Radar Chip
Granted: July 11, 2024
Application Number:
20240235535
Disclosed are a frequency multiplier, a signal transmitter and a radar chip. The frequency multiplier includes a signal generator that is configured to receive an FMCW signal and output a square wave signal at a frequency same as a frequency of the FMCW signal; and a third harmonic amplifier that is coupled to the signal generator and is configured to amplify a third harmonic wave in the square wave signal and output a frequency-tripled FMCW signal. The above-mentioned solution can…
Circuits And Methods For Tampering Detection
Granted: July 4, 2024
Application Number:
20240220671
An integrated circuit includes an anti-tamper circuit having a resistor. The resistor includes conductors in a conductive layer of the integrated circuit. Each of the conductors extends across a width of the integrated circuit. The conductors are spaced apart across a length of the integrated circuit. The anti-tamper circuit generates an output signal indicative of changes in a resistance of the resistor caused by tampering that affects the conductors.
Systems And Methods For Configuring Signal Paths In An Interposer Between Integrated Circuits
Granted: June 27, 2024
Application Number:
20240213985
A circuit system includes an interposer comprising conductors and switch circuits coupled to the conductors, a first integrated circuit die coupled to the interposer, and a second integrated circuit die coupled to the interposer. The first integrated circuit die comprises a primary controller circuit for configuring the switch circuits. The second integrated circuit die comprises a secondary controller circuit. The primary controller circuit configures configurable logic circuits in the…
Techniques For Coarse Grained And Fine Grained Configurations Of Configurable Logic Circuits
Granted: June 13, 2024
Application Number:
20240193331
An integrated circuit includes configurable logic circuit blocks that are configurable with a first configuration bitstream according to a coarse grained configuration. The coarse grained configuration implements an aggregate circuit structure of the configurable logic circuit blocks. The configurable logic circuit blocks are configurable with a second configuration bitstream according to a fine grained configuration. A total number of the first and the second configuration bits is fewer…
Circuits And Methods For Receiving Data Signals Having Different Common-Mode Voltages
Granted: May 30, 2024
Application Number:
20240178801
A receiver circuit includes a first sense amplifier circuit that generates a first data signal based on a second data signal that has a first common-mode voltage during a first mode of operation. The receiver circuit includes a second sense amplifier circuit that generates a third data signal based on a fourth data signal that has a second common-mode voltage less than the first common-mode voltage during a second mode of operation. The receiver circuit includes a switch circuit that…
CALIBRATION CIRCUIT AND METHOD, PHASE-SHIFT CIRCUIT, RADIO-FREQUENCY TRANSCEIVER CIRCUIT, RADAR AND DEVICE
Granted: May 30, 2024
Application Number:
20240175980
A calibration circuit and a calibration method for a phase shifter, a phase-shift circuit, a radio frequency transmitting circuit, a radio frequency receiving circuit, a radar sensor and an electronic device are provided. The calibration circuit for the phase shifter includes a phase acquisition circuit and a phase calibration circuit, the phase acquisition circuit coupled to the phase shifter is configured to modulate a radio frequency sample signal acquired from the phase shifter using…
Active Interposers For Migration Of Packages
Granted: May 16, 2024
Application Number:
20240162189
An active interposer device includes a multiplexer circuit configurable to provide a first signal from a first integrated circuit to an external terminal of the active interposer device in a first configuration of the active interposer device. The multiplexer circuit is further configurable to provide a second signal from a second integrated circuit to the external terminal in a second configuration of the active interposer device. The second integrated circuit is larger than the first…
DATA COMPRESSION METHOD AND APPARATUS, AND DATA DECOMPRESSION METHOD AND APPARATUS
Granted: May 16, 2024
Application Number:
20240160350
A data compression method, apparatus, a data decompression method and apparatus are provided. In the methods and apparatuses, on the basis of an average effective bit value of data in a data block and an average storage bit width occupied by the remaining part of each item of data in the compressed data block, compression of a fixed compression rate is implemented on the remaining part of the data, reducing the storage space occupied by the remaining part of the data whilst allowing for…
DATA COMPRESSION METHOD AND APPARATUS, AND DATA DECOMPRESSION METHOD AND APPARATUS
Granted: April 25, 2024
Application Number:
20240137043
A data compression method, apparatus, a data decompression method and apparatus are provided. In the methods an apparatuses, on the basis of an average effective bit value of data in a data block and an average storage bit width occupied by e remaining part of each item of data in the compressed data block, compression of a fixed compression rate is implemented on the remaining part of the data, reducing the storage space occupied by the remaining part of the data whilst allowing for…
Techniques For Storing States Of Signals In Configurable Storage Circuits
Granted: April 25, 2024
Application Number:
20240137026
An integrated circuit includes a logic circuit block that includes a first adaptive logic module configurable to store a first state of a first signal received from a device-under-test in a first register, a second adaptive logic module configurable to store a second state of a second signal in a second register during a user mode of the integrated circuit simultaneously with the first state of the first signal being stored in the first register, and a third adaptive logic module…
Frequency Multiplier, Signal Transmitter and Radar Chip
Granted: April 25, 2024
Application Number:
20240137013
Disclosed are a frequency multiplier, a signal transmitter and a radar chip. The frequency multiplier includes a signal generator that is configured to receive an FMCW signal and output a square wave signal at a frequency same as a frequency of the FMCW signal; and a third harmonic amplifier that is coupled to the signal generator and is configured to amplify a third harmonic wave in the square wave signal and output a frequency-tripled FMCW signal. The above-mentioned solution can…
METHOD AND APPARATUS FOR DETERMINING NOISE FLOOR ESTIMATED VALUE, TARGET DETECTION METHOD AND APPARATUS, AND ELECTRONIC DEVICE
Granted: April 25, 2024
Application Number:
20240134001
Embodiments of the present disclosure provide a method and apparatus for determining a noise floor estimated value, a target detection method and apparatus, and an electronic device. The determining method comprises: obtaining a two-dimensional Fourier data plane corresponding to a linear frequency modulation continuous wave, wherein the two-dimensional Fourier data plane comprises a distance dimension and a Doppler dimension, and the distance dimension comprises a plurality of distances…
METHOD AND APPARATUS FOR DETERMINING DATA STORAGE BIT WIDTH, AND METHOD FOR STORING INDEX DATA
Granted: April 18, 2024
Application Number:
20240126683
A method and apparatus for determining a data storage bit width and a method for storing exponential data. The method for determining the data storage bit width includes: acquiring data to be stored, the number of which is at least 4; dividing the data into blocks according to a preset number 2n, n is an integer greater than or equal to 2; determining effective bit numbers and a value of a maximum effective bit number in a block; dividing data in the block equally into a first sub-block…
