Techniques For Configuring Computing Nodes In A Computing System
Granted: April 18, 2024
Application Number:
20240126969
An integrated circuit includes logic circuits that are configurable by a bitstream of configuration data to perform a computing service requested in a computing system. The integrated circuit communicates with a central processing unit in the computing system according to interface features indicated by meta-data provided to the central processing unit to perform the computing service.
METHOD AND APPARATUS FOR DETERMINING DATA STORAGE BIT WIDTH, AND METHOD FOR STORING INDEX DATA
Granted: April 18, 2024
Application Number:
20240126683
A method and apparatus for determining a data storage bit width and a method for storing exponential data. The method for determining the data storage bit width includes: acquiring data to be stored, the number of which is at least 4; dividing the data into blocks according to a preset number 2n, n is an integer greater than or equal to 2; determining effective bit numbers and a value of a maximum effective bit number in a block; dividing data in the block equally into a first sub-block…
INTERFERENCE SIGNAL DETECTION METHOD AND APPARATUS, AND INTEGRATED CIRCUIT, RADIO DEVICE AND TERMINAL
Granted: April 18, 2024
Application Number:
20240125891
An interference signal detection method, apparatus, integrated circuit, radio device and terminal are disclosed, wherein, the method includes: transmitting a target signal based on a radar, receiving N frames of echo signals, obtaining N pieces of 2D FFT plane information according to the N frames of echo signals, wherein any piece of 2D FFT plane information includes power information corresponding to a range and a velocity, and detecting whether an echo signal is interfered according…
DATA PROCESSING METHOD AND APPARATUS, AND RADAR SENSOR
Granted: April 11, 2024
Application Number:
20240118385
A data processing method is provided, which can be applied to calculating a histogram of a preset data sequence. Each piece of data in the preset data sequence comprises an exponential part and a mantissa part. The method comprises: performing normalization processing on the preset data sequence to obtain a first index and a first mantissa of each data; according to the first index and the first mantissa of each data, generating a register address; and according to the register address,…
Techniques For Managing Packet Scheduling From Queue Circuits
Granted: April 4, 2024
Application Number:
20240113985
An integrated circuit includes queue circuits for storing packets, a scheduler circuit that schedules the packets received from the queue circuits to be provided in an output, and a traffic manager circuit that disables one of the queue circuits from transmitting any of the packets to the scheduler circuit based at least in part on a bandwidth in the output scheduled for a subset of the packets received from the one of the queue circuits.
Circuits And Methods For Converting Between Data Formats And Data Filtering
Granted: April 4, 2024
Application Number:
20240113730
An integrated circuit includes conversion circuitry for converting first data in a first data format optimized for efficient data storage into second data in a second data format optimized for processing by a processing circuit. The integrated circuit also includes filter circuitry for filtering the second data to generate filtered data in the second data format. The integrated circuit outputs the filtered data for processing by the processing circuit.
Techniques For Shifting Signal Transmission To Compensate For Defects In Pads In Integrated Circuits
Granted: April 4, 2024
Application Number:
20240113014
An integrated circuit includes first external conductive pads, second external conductive pads, and third external conductive pads. The second external conductive pads are between the first external conductive pads and the third external conductive pads. Repair group circuitry is configurable to shift signal transmission away from one of the first external conductive pads to one of the third external conductive pads if the one of the first external conductive pads has a defect.
Techniques For Configuring Repeater Circuits In Active Interconnection Devices
Granted: April 4, 2024
Application Number:
20240111703
An active interconnection device has a repeater circuit that includes a storage circuit. The storage circuit is coupled to store a configuration bit for configuring the repeater circuit to transmit a signal between a first integrated circuit die and a second integrated circuit die. The storage circuit is coupled to receive the configuration bit through a conductor during a configuration mode. A buffer circuit in the repeater circuit is configurable to transmit the signal through the…
ON-BOARD ANTENNA, RADIO DEVICE, AND ELECTRONIC APPARATUS
Granted: July 27, 2023
Application Number:
20230238706
An onboard antenna, a radio equipment and an electronic device. The onboard antenna includes a dielectric substrate, an antenna and a metal block, wherein the antenna is located on the dielectric substrate, a projection of the metal block on a plane where the dielectric substrate is located is not overlapped with a projection of the antenna on the plane where the dielectric substrate is located, the metal block is located on the dielectric substrate in a polarization direction of the…
ATTENUATION APPARATUS AND TEST SYSTEM
Granted: June 29, 2023
Application Number:
20230208000
An attenuation apparatus and a test system. The attenuation apparatus includes a signal transmission channel and at least one radiation loss structure, wherein the signal transmission channel is configured to perform transmission attenuation on the energy of a transmitted signal; the radiation loss structure is arranged in the signal transmission channel; the radiation loss structure has a first operating state and a second operating state; when the radiation loss structure is in the…
MICROSTRIP ANTENNA, ANTENNA ARRAY, RADAR, AND VEHICLE
Granted: June 22, 2023
Application Number:
20230198134
A microstrip antenna, an antenna array, a radar, and a vehicle are provided. The microstrip antenna includes: a dielectric layer, and a metal layer and a ground plane layer disposed at two sides of the dielectric layer, wherein the metal layer includes a first radiation patch and a feeding portion; a length of a long side edge of the first radiation patch is determined based on an operating wavelength of the microstrip antenna, and a length of a short side edge of the first radiation…
MULTI-ACCESS MEMORY SYSTEM AND A METHOD TO MANUFACTURE THE SYSTEM
Granted: April 8, 2021
Application Number:
20210104486
A multiple memory access system is disclosed. The system includes a first die disposed on a package substrate. A second die is stacked above the first die. The first die, the second die and the package substrate form a first package. An IC is placed within a close proximity of the first package where the first die communicates with the second die at a first data rate while the first die communicates with the IC at a second data rate. The first data rate is higher than the second data…
Apparatus For Flexible Electronic Interfaces And Associated Methods
Granted: January 21, 2021
Application Number:
20210021268
A semiconductor die includes at least one flexible interface block. The flexible interface block includes at least one interconnect, and at least one buffer coupled to the at least one interconnect. The flexible interface block further includes a routing interface coupled to circuitry integrated in the semiconductor die, and a controller coupled to provide communication between the routing interface and the at least one buffer.
TEMPER EVIDENT INJECTOR LOCK AND A LOCKING METHOD
Granted: August 20, 2020
Application Number:
20200261663
A two-stage temper evident injector lock with a security indicator on the two-stage temper evident injector lock and a method of locking the two-stage temper evident injector lock, which has been developed for guaranteeing a security for that a dosage of a fluid contained in the medical injectors (syringes) that are filled with the medications prepared at medication preparation areas, and mostly with specific fluids is not altered before being applied to a subject.
COAXIAL BREATHING CIRCUIT SYSTEMS HAVING A LUNG PRESSURE MEASUREMENT PORT AND CLOSED SYSTEM WATER TRAP WHICH CAN BE DRAINED WITH AN ENJECTOR
Granted: June 25, 2020
Application Number:
20200197648
The invention relates to providing novel functions to the coaxial breathing circuits which at present do not comprise water traps, by adding a closed system water trap designed to have an inkwell shape and a lung pressure measurement port to said circuits wherein the fluid collected in the bottle section can be discharged without having to open the bottle by means of a drainage luer port located at the base of the bottle and a needleless apparatus that has been inserted into the port,…
SCALABLE 2.5D INTERFACE CIRCUITRY
Granted: March 5, 2020
Application Number:
20200073851
A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to…
Techniques For Signal Skew Compensation
Granted: September 5, 2019
Application Number:
20190273504
An integrated circuit includes a signal network and a phase detector circuit. The signal network includes an adjustable delay circuit. The adjustable delay circuit is coupled at an intersection in the signal network between branches of the signal network. The signal network generates a first signal at a first leaf node of the signal network in response to a second signal. The signal network generates a third signal at a second leaf node of the signal network in response to the second…
DENORMALIZATION IN MULTI-PRECISION FLOATING-POINT ARITHMETIC CIRCUITRY
Granted: August 15, 2019
Application Number:
20190250886
The present embodiments relate to integrated circuits with floating-point arithmetic circuitry that handles normalized and denormalized floating-point numbers. The floating-point arithmetic circuitry may include a normalization circuit and a rounding circuit, and the floating-point arithmetic circuitry may generate a first result in form of a normalized, unrounded floating-point number and a second result in form of a normalized, rounded floating-point number. If desired, the…
METHOD FOR DISTRIBUTING A LOAD IN A MULTI RADIO ACCESS TECHNOLOGY HETEROGENEOUS NETWORK
Granted: March 7, 2019
Application Number:
20190075570
A method for distributing the traffic load in a multi radio access technology heterogeneous network, the network including macrocells operating in a first sub-6 GHz band, and minicells that can operate in the sub-6 GHz band and in a millimeter band. The distribution of the traffic is carried out with an association strategy that calls upon, on the first hand, a first bias (QT) in order to favour the association with the base stations of the minicells/macrocells and a second bias (QR) in…
Techniques For Protecting Security Features of Integrated Circuits
Granted: January 24, 2019
Application Number:
20190026497
An integrated circuit includes a control circuit and a one-time programmable circuit. The control circuit determines if the one-time programmable circuit is programmed in response to an attempt to access a mode of the integrated circuit after the integrated circuit powers up. The control circuit generates a signal to indicate to a user of the integrated circuit that the mode of the integrated circuit has been previously accessed if the control circuit determines that the one-time…
