Apparatus for Improved Encoding and Associated Methods
Granted: May 1, 2014
Application Number:
20140119388
An apparatus includes an encoder adapted to encode data bits for transmission via a communication link. The encoder includes a logic circuit. The logic circuit is adapted to perform a logic operation on a pattern of bits and the data bits in order to reduce a run-length of the data bits.
TECHNIQUES AND CIRCUITRY FOR CONFIGURING AND CALIBRATING AN INTEGRATED CIRCUIT
Granted: May 1, 2014
Application Number:
20140118026
A technique for configuring an integrated circuit includes receiving configuration data from an external element with an interface circuit. The configuration data may include an identification field and an instruction for configuring a logic block. Configuration circuitry may be used to identify the logic block to be configured based on the identification field. A storage element in the identified logic block is configured by the configuration circuitry based on the instruction.
METHODS AND APPARATUS FOR BUILDING BUS INTERCONNECTION NETWORKS USING PROGRAMMABLE INTERCONNECTION RESOURCES
Granted: April 24, 2014
Application Number:
20140111247
Integrated circuits may include logic regions configurable to perform custom functions. Interconnects may be used to route signals throughout the integrated circuit. The logic region may be coupled to input selection circuitry for selecting and providing input signals from the interconnects to the logic regions and to output selection and routing circuitry for selecting and transmitting output signals over interconnects to other logic regions. Bypass circuitry may provide direct access…
Simulation Tool for High-Speed Communications Links
Granted: April 17, 2014
Application Number:
20140107997
A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer…
METHOD AND SYSTEM FOR MANAGING HARDWARE RESOURCES TO IMPLEMENT SYSTEM FUNCTIONS USING AN ADAPTIVE COMPUTING ARCHITECTURE
Granted: April 10, 2014
Application Number:
20140101410
An adaptable integrated circuit is disclosed having a plurality of heterogeneous computational elements coupled to an interconnection network. The interconnection network changes interconnections between the plurality of heterogeneous computational elements in response to configuration information. A first group of computational elements is allocated to form a first version of a functional unit to perform a first function by changing interconnections in the interconnection network…
3D MEMORY BASED ADDRESS GENERATOR
Granted: April 10, 2014
Application Number:
20140101409
Systems and methods are disclosed for reducing memory usage and increasing the throughput in variable-size Fast Fourier Transform (FFT) architectures. In particular, 3D symmetric virtual memory is disclosed to exploit the structure inherent in variable-size FFT computations. Data samples may be written to and read from the 3D symmetric virtual memory in a specific sequence of coordinates that exploits the structure inherent in variable-size FFT computations. Memory locations in the 3D…
METHOD FOR FINDING STARTING BIT OF REFERENCE FRAMES FOR AN ALTERNATING-PARITY REFERENCE CHANNEL
Granted: April 10, 2014
Application Number:
20140101350
The present invention discloses a method for locating the reference frames of the reference lane on the transmitting data bus. The present invention addresses this object by disclosing a method whereby the relationship between the size of the reference frame transmitted over the reference lane and the width of the data bus is such that the reference frame is bit-shifted automatically until it is aligned with the data bus.
Side Stack Interconnection for Integrated Circuits and The Like
Granted: April 10, 2014
Application Number:
20140097544
In an illustrative embodiment, a plurality of integrated circuits are stacked one on top of the other in a block. A plurality of leads on each integrated circuit is made accessible on a first side of the block. An insulating layer is formed on the first side of the block; electrically conducting vias are formed in the insulating layer and coupled to the leads; a conducting layer is formed on the insulating layer and coupled to the conducting vias; and conducting paths are formed in the…
MEMORY ELEMENTS WITH RELAY DEVICES
Granted: March 27, 2014
Application Number:
20140085967
Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may…
METHOD AND APPARATUS FOR SECURING PROGRAMMING DATA OF A PROGRAMMABLE DEVICE
Granted: March 27, 2014
Application Number:
20140089677
Configuration data for a programmable integrated circuit device is at least partially encrypted according to at least one encryption scheme. A plurality of key stores store a plurality of decryption keys for the at least one encryption scheme. Control circuitry identifies a required key from the at least partially encrypted configuration data and generates a key selection signal. Key selection circuitry responsive to the key selection signal reads the plurality of key stores and provides…
MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE, DEDICATED CONNECTIONS BETWEEN MODULES OF THE CIRCUITRY
Granted: March 20, 2014
Application Number:
20140082035
Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks…
CLOCK SIGNAL NETWORKS FOR STRUCTURED ASIC DEVICES
Granted: March 20, 2014
Application Number:
20140077839
Clock, distribution circuitry for a structured ASIC device includes a deterministic portion, and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock…
Methods and Apparatus for Adapting Pipeline Stage Latency Based on Instruction Type
Granted: March 13, 2014
Application Number:
20140075157
Processor pipeline controlling techniques are described which take advantage of the variation in critical path lengths of different instructions to achieve increased performance. By examining a processor's instruction set and execution unit implementation's critical timing paths, instructions are classified into speed classes. Based on these speed classes, one pipeline is presented where hold signals are used to dynamically control the pipeline based on the instruction class in…
Methods and Apparatus for Providing Bit-Reversal and Multicast Functions Utilizing DMA Controller
Granted: March 13, 2014
Application Number:
20140075081
Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal…
MULTIPLE DATA RATE INTERFACE ARCHITECTURE
Granted: February 20, 2014
Application Number:
20140049287
Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.
SHIELDING STRUCTURE FOR TRANSMISSION LINES
Granted: February 20, 2014
Application Number:
20140048915
A shielding structure for transmission lines comprises first and second comb-like structures defined in a first metallization layer on an integrated circuit, the teeth of each comb-like structure extending toward the other comb-like structure; a first plurality of electrically conducting vias extending upward from the first comb-like structure; a second plurality of electrically conducting vias extending upward from the second comb-like structure; first and second planar structures in a…
Method and Apparatus for Implementing Soft Constraints in Tools Used for Designing Programmable Logic Devices
Granted: February 13, 2014
Application Number:
20140047405
A method for designing a system on a target device utilizing programmable logic devices (PLDs) includes generating options for utilizing resources on the PLDs in response to user specified constraints. The options for utilizing the resources on the PLDs are refined independent of the user specified constraints.
RECONFIGURABLE LOGIC BLOCK
Granted: February 13, 2014
Application Number:
20140047401
A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a…
Techniques for Varying a Periodic Signal Based on Changes in a Data Rate
Granted: February 6, 2014
Application Number:
20140037033
A circuit includes phase detection, frequency adjustment, sampler, and control circuits. The phase detection circuit compares phases of first and second periodic signals to generate a control signal. The frequency adjustment circuit adjusts a frequency of the second periodic signal and a frequency of a third periodic signal based on the control signal. The sampler circuit samples a data signal to generate a sampled data signal in response to the third periodic signal. The control circuit…
SYSTEM AND METHOD FOR CREATING A SCALABLE MONOLITHIC PACKET PROCESSING ENGINE
Granted: February 6, 2014
Application Number:
20140040515
A novel and efficient method is described that creates a monolithic high capacity Packet Engine (PE) by connecting N lower capacity Packet Engines (PEs) via a novel Chip-to-Chip (C2C) interface. The C2C interface is used to perform functions, such as memory bit slicing and to communicate shared information, and enqueue/dequeue operations between individual PEs.
