3D BUILT-IN SELF-TEST SCHEME FOR 3D ASSEMBLY DEFECT DETECTION
Granted: July 3, 2014
Application Number:
20140189456
Techniques and mechanisms are provided for an improved built in self-test (BIST) mechanism for 3D assembly defect detection. According to an embodiment of the present disclosure, the described mechanisms and techniques can function to detect defects in interconnects which vertically connect different layers of a 3D device, as well as to detect defects on a 2D layer of a 3D integrated circuit. Additionally, according to an embodiment of the present disclosure, techniques and mechanisms…
FORWARD ERROR CORRECTION WITH CONFIGURABLE LATENCY
Granted: July 3, 2014
Application Number:
20140189446
A method of performing forward error correction with configurable latency, where a configurable latency algorithm evaluates a target Bit Error Rate (BER) against an actual BER and adjusts the size of a configurable buffer such that the target BER may be achieved when utilizing the smallest buffer size possible. When errors are corrected without the utilization of each of the configurable buffer locations, the algorithm reduces the size of the buffer by y buffer locations; the algorithm…
System and Method for Scheduling and Arbitrating Events in Computing and Networking
Granted: June 26, 2014
Application Number:
20140181126
A method for high-speed scheduling and arbitration of events for computing and networking is disclosed. The method includes the software and hardware implementation of a unique data structure, known as a pile, for scheduling and arbitration of events. According to the method, events are stored in loosely sorted order in piles, with the next event to be processed residing in the root node of the pile. The pipelining of the insertion and removal of events from the piles allows for…
HETEROGENEOUS HIGH-SPEED SERIAL INTERFACE SYSTEM ARCHITECTURE
Granted: June 26, 2014
Application Number:
20140176188
One embodiment relates to an integrated circuit having a plurality of four-channel serial interface modules. Each of the plurality of four-channel serial interface modules includes a first physical medium attachment (PMA) channel circuit, a second PMA channel circuit adjacent to the first PMA channel circuit, a third PMA channel circuit adjacent to the second PMA channel circuit, a fourth PMA channel circuit adjacent to the third PMA channel circuit, and at least one phase-locked loop…
INTEGRATED CIRCUIT DEVICE WITH STITCHED INTERPOSER
Granted: June 26, 2014
Application Number:
20140175666
Systems, methods, and devices are provided to enable an integrated circuit device of relatively higher capacity. Such an integrated circuit device may include at least two component integrated circuits that communicate with one another. Specifically, the component integrated circuits may communicate through a “stitched silicon interposer” that is larger than a reticle limit of the lithography system used to manufacture the interposer. To achieve this larger size, the stitched silicon…
PROCESSORS AND COMPILING METHODS FOR PROCESSORS
Granted: June 19, 2014
Application Number:
20140173575
A compiling method compiles an object program to be executed by a processor having a plurality of execution units operable in parallel. In the method a first availability chain is created from a producer instruction (p1), scheduled for execution by a first one of the execution units (20: AGU), to a first consumer instruction (c1), scheduled for execution by a second one of the execution units (22: EXU) and requiring a value produced by the said producer instruction. The first…
Methods and Apparatus for Storing Expanded Width Instructions in a VLIW Memory for Deferred Execution
Granted: June 19, 2014
Application Number:
20140173253
Techniques are described for decoupling fetching of an instruction stored in a main program memory from earliest execution of the instruction. An indirect execution method and program instructions to support such execution are addressed. In addition, an improved indirect deferred execution processor (DXP) VLIW architecture is described which supports a scalable array of memory centric processor elements that do not require local load and store units.
APPARATUS AND METHODS FOR EQUALIZER ADAPTATION
Granted: June 19, 2014
Application Number:
20140169439
One embodiment relates to an equalizer circuit for a data link. The equalizer circuit including a continuous-time linear equalizer, a first circuit loop, and a second circuit loop. The continuous-time linear equalizer receives a received signal and outputs an equalized signal. The first circuit loop determines a first average signal amplitude. The first average signal amplitude may be an average signal amplitude of the equalized signal. The second circuit loop a second average signal…
MEMORY ELEMENTS WITH STACKED PULL-UP DEVICES
Granted: June 19, 2014
Application Number:
20140169074
Integrated circuits with memory cells are provided. A memory cell may include first and second cross-coupled inverting circuits configured to store a single data bit. The first inverting circuit may have an output serving as a first data storage node for the memory cell, whereas the second inverting circuit may have an output serving as a second data storage node for the memory cell. Access transistors may be coupled between the first and second data storage nodes and corresponding data…
ANTENNA DIODE CIRCUITRY AND METHOD OF MANUFACTURE
Granted: June 12, 2014
Application Number:
20140159157
An integrated circuit with an antenna diode is described. The integrated circuit includes a substrate, a transistor, first and second diffusion regions, and a dummy gate. The transistor and the first and second diffusion regions may be formed within the substrate. The transistor has its gate structure disposed on the substrate. The dummy gate structure may be disposed on a region of the substrate such that it separates the first diffusion region from the second diffusion region. The…
METHOD AND APPARATUS FOR TRANSLATING GRAPHICAL SYMBOLS INTO QUERY KEYWORDS
Granted: June 5, 2014
Application Number:
20140156703
Computer equipment operable to translate a graphical symbol into keywords is disclosed. The computer equipment includes a database of keywords. An input analyzer tool may be used to retrieve a list of keywords from the database based on the graphical symbol. The input analyzer tool may be implemented using processing circuitry that accepts graphical input and performs symbol translation to formulate a search query related to the graphical input. An information search may be performed…
APPARATUS FOR AUTOMATICALLY CONFIGURED INTERFACE AND ASSOCIATED METHODS
Granted: May 29, 2014
Application Number:
20140145758
An integrated circuit (IC) includes a first circuit implemented using programmable circuitry of the IC, and a second circuit implemented using hardened circuitry of the IC. The IC further includes a configurable interface circuit to couple the first circuit to the second circuit using ready/valid signaling with a configurable ready-latency value.
MEMORY INTERFACE CIRCUITRY WITH IMPROVED TIMING MARGINS
Granted: May 29, 2014
Application Number:
20140145756
Integrated circuits may include memory interface circuitry that communicates with memory. The memory interface circuitry may include latch circuitry that receives a data strobe enable signal from the memory controller and latches the data strobe enable signal using a data strobe signal received from the memory. The integrated circuit may include logic circuitry that gates the data strobe signal using the latched data strobe enable signal. The logic circuitry may pass the data strobe…
BIDIRECTIONAL WAVELENGTH CROSS CONNECT ARCHITECTURES USING WAVELENGTH ROUTING ELEMENTS
Granted: May 22, 2014
Application Number:
20140140696
Bidirectional wavelength cross connects include a plurality of ports, each configured to receive an input optical signals, each input optical signal having a plurality of spectral bands. At least one of the plurality of ports is disposed to simultaneously transmit an output optical signal having at least one of the spectral bands. A plurality of wavelength routing elements are configured to selectively route input optical signal spectral bands to output optical signals.
Methods for Testing Network Circuitry
Granted: May 15, 2014
Application Number:
20140136905
A method of operating a test equipment system that is coupled to network circuitry is described. The method displays only selected information. Furthermore, the method may display the selected information in a manner as to allow a user of the test equipment to easily identify errors in the network circuitry. The method may select the information to be displayed by processing received signals according to a stacked protocol hierarchical structure.
APPARATUS AND METHODS FOR ADAPTIVE RECEIVER DELAY EQUALIZATION
Granted: May 15, 2014
Application Number:
20140133529
Disclosed are apparatus and methods for adaptive receiver delay equalization. One embodiment relates to a method for adaptive receiver delay equalization. Filtered positive and negative polarity signals are generated by a first variable-delay filter and a second variable-delay filter, respectively. A delay difference is determined between the filtered positive and negative polarity signals, and a skew-indication signal is generated based on the delay difference. A delay control signal is…
PROGRAMMABLE LOGIC DEVICE WITH INTEGRATED NETWORK-ON-CHIP
Granted: May 8, 2014
Application Number:
20140126572
Systems and methods for providing a Network-On-Chip (NoC) structure on an integrated circuit for high-speed data passing. In some aspects, the NoC structure includes multiple NoC stations with a hard-IP interface having a bidirectional connection to local components of the integrated circuit. In some aspects, the NoC stations have a soft-IP interface that supports the hard-IP interface of the NoC station.
SYSTEMS AND METHODS FOR INTERFACING BETWEEN HARD LOGIC AND SOFT LOGIC IN A HYBRID INTEGRATED DEVICE
Granted: May 8, 2014
Application Number:
20140125379
Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that includes interconnects between hard logic and soft logic, which enable signals to be selectively routed between the inputs and outputs of hard logic blocks and soft logic modules. The interconnects allow for certain hard logic blocks to be bypassed in favor of soft logic functionality. Moreover,…
TECHNIQUES AND CIRCUITRY FOR CONFIGURING AND CALIBRATING AN INTEGRATED CIRCUIT
Granted: May 1, 2014
Application Number:
20140118026
A technique for configuring an integrated circuit includes receiving configuration data from an external element with an interface circuit. The configuration data may include an identification field and an instruction for configuring a logic block. Configuration circuitry may be used to identify the logic block to be configured based on the identification field. A storage element in the identified logic block is configured by the configuration circuitry based on the instruction.
APPARATUS FOR IMPROVED ENCODING AND ASSOCIATED METHODS
Granted: May 1, 2014
Application Number:
20140119486
An apparatus includes an encoder adapted to encode data bits for transmission via a communication link using pulse amplitude modulation (PAM). The encoder includes a logic circuit. The logic circuit is adapted to perform a logic operation on a pattern of bits and the data bits in order to reduce a run-length and/or improve the DC balance of the data bits.
