MEMORY ELEMENTS WITH STACKED PULL-UP DEVICES
Granted: June 19, 2014
Application Number:
20140169074
Integrated circuits with memory cells are provided. A memory cell may include first and second cross-coupled inverting circuits configured to store a single data bit. The first inverting circuit may have an output serving as a first data storage node for the memory cell, whereas the second inverting circuit may have an output serving as a second data storage node for the memory cell. Access transistors may be coupled between the first and second data storage nodes and corresponding data…
ANTENNA DIODE CIRCUITRY AND METHOD OF MANUFACTURE
Granted: June 12, 2014
Application Number:
20140159157
An integrated circuit with an antenna diode is described. The integrated circuit includes a substrate, a transistor, first and second diffusion regions, and a dummy gate. The transistor and the first and second diffusion regions may be formed within the substrate. The transistor has its gate structure disposed on the substrate. The dummy gate structure may be disposed on a region of the substrate such that it separates the first diffusion region from the second diffusion region. The…
METHOD AND APPARATUS FOR TRANSLATING GRAPHICAL SYMBOLS INTO QUERY KEYWORDS
Granted: June 5, 2014
Application Number:
20140156703
Computer equipment operable to translate a graphical symbol into keywords is disclosed. The computer equipment includes a database of keywords. An input analyzer tool may be used to retrieve a list of keywords from the database based on the graphical symbol. The input analyzer tool may be implemented using processing circuitry that accepts graphical input and performs symbol translation to formulate a search query related to the graphical input. An information search may be performed…
APPARATUS FOR AUTOMATICALLY CONFIGURED INTERFACE AND ASSOCIATED METHODS
Granted: May 29, 2014
Application Number:
20140145758
An integrated circuit (IC) includes a first circuit implemented using programmable circuitry of the IC, and a second circuit implemented using hardened circuitry of the IC. The IC further includes a configurable interface circuit to couple the first circuit to the second circuit using ready/valid signaling with a configurable ready-latency value.
MEMORY INTERFACE CIRCUITRY WITH IMPROVED TIMING MARGINS
Granted: May 29, 2014
Application Number:
20140145756
Integrated circuits may include memory interface circuitry that communicates with memory. The memory interface circuitry may include latch circuitry that receives a data strobe enable signal from the memory controller and latches the data strobe enable signal using a data strobe signal received from the memory. The integrated circuit may include logic circuitry that gates the data strobe signal using the latched data strobe enable signal. The logic circuitry may pass the data strobe…
BIDIRECTIONAL WAVELENGTH CROSS CONNECT ARCHITECTURES USING WAVELENGTH ROUTING ELEMENTS
Granted: May 22, 2014
Application Number:
20140140696
Bidirectional wavelength cross connects include a plurality of ports, each configured to receive an input optical signals, each input optical signal having a plurality of spectral bands. At least one of the plurality of ports is disposed to simultaneously transmit an output optical signal having at least one of the spectral bands. A plurality of wavelength routing elements are configured to selectively route input optical signal spectral bands to output optical signals.
Methods for Testing Network Circuitry
Granted: May 15, 2014
Application Number:
20140136905
A method of operating a test equipment system that is coupled to network circuitry is described. The method displays only selected information. Furthermore, the method may display the selected information in a manner as to allow a user of the test equipment to easily identify errors in the network circuitry. The method may select the information to be displayed by processing received signals according to a stacked protocol hierarchical structure.
APPARATUS AND METHODS FOR ADAPTIVE RECEIVER DELAY EQUALIZATION
Granted: May 15, 2014
Application Number:
20140133529
Disclosed are apparatus and methods for adaptive receiver delay equalization. One embodiment relates to a method for adaptive receiver delay equalization. Filtered positive and negative polarity signals are generated by a first variable-delay filter and a second variable-delay filter, respectively. A delay difference is determined between the filtered positive and negative polarity signals, and a skew-indication signal is generated based on the delay difference. A delay control signal is…
SYSTEMS AND METHODS FOR INTERFACING BETWEEN HARD LOGIC AND SOFT LOGIC IN A HYBRID INTEGRATED DEVICE
Granted: May 8, 2014
Application Number:
20140125379
Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that includes interconnects between hard logic and soft logic, which enable signals to be selectively routed between the inputs and outputs of hard logic blocks and soft logic modules. The interconnects allow for certain hard logic blocks to be bypassed in favor of soft logic functionality. Moreover,…
PROGRAMMABLE LOGIC DEVICE WITH INTEGRATED NETWORK-ON-CHIP
Granted: May 8, 2014
Application Number:
20140126572
Systems and methods for providing a Network-On-Chip (NoC) structure on an integrated circuit for high-speed data passing. In some aspects, the NoC structure includes multiple NoC stations with a hard-IP interface having a bidirectional connection to local components of the integrated circuit. In some aspects, the NoC stations have a soft-IP interface that supports the hard-IP interface of the NoC station.
ADAPTIVE INTEGRATED CIRCUITRY WITH HETEROGENEOUS AND RECONFIGURABLE MATRICES OF DIVERSE AND ADAPTIVE COMPUTATIONAL UNITS HAVING FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS
Granted: May 1, 2014
Application Number:
20140122764
The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition,…
APPARATUS FOR IMPROVED ENCODING AND ASSOCIATED METHODS
Granted: May 1, 2014
Application Number:
20140119486
An apparatus includes an encoder adapted to encode data bits for transmission via a communication link using pulse amplitude modulation (PAM). The encoder includes a logic circuit. The logic circuit is adapted to perform a logic operation on a pattern of bits and the data bits in order to reduce a run-length and/or improve the DC balance of the data bits.
Apparatus for Improved Encoding and Associated Methods
Granted: May 1, 2014
Application Number:
20140119388
An apparatus includes an encoder adapted to encode data bits for transmission via a communication link. The encoder includes a logic circuit. The logic circuit is adapted to perform a logic operation on a pattern of bits and the data bits in order to reduce a run-length of the data bits.
TECHNIQUES AND CIRCUITRY FOR CONFIGURING AND CALIBRATING AN INTEGRATED CIRCUIT
Granted: May 1, 2014
Application Number:
20140118026
A technique for configuring an integrated circuit includes receiving configuration data from an external element with an interface circuit. The configuration data may include an identification field and an instruction for configuring a logic block. Configuration circuitry may be used to identify the logic block to be configured based on the identification field. A storage element in the identified logic block is configured by the configuration circuitry based on the instruction.
METHODS AND APPARATUS FOR BUILDING BUS INTERCONNECTION NETWORKS USING PROGRAMMABLE INTERCONNECTION RESOURCES
Granted: April 24, 2014
Application Number:
20140111247
Integrated circuits may include logic regions configurable to perform custom functions. Interconnects may be used to route signals throughout the integrated circuit. The logic region may be coupled to input selection circuitry for selecting and providing input signals from the interconnects to the logic regions and to output selection and routing circuitry for selecting and transmitting output signals over interconnects to other logic regions. Bypass circuitry may provide direct access…
Simulation Tool for High-Speed Communications Links
Granted: April 17, 2014
Application Number:
20140107997
A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer…
Side Stack Interconnection for Integrated Circuits and The Like
Granted: April 10, 2014
Application Number:
20140097544
In an illustrative embodiment, a plurality of integrated circuits are stacked one on top of the other in a block. A plurality of leads on each integrated circuit is made accessible on a first side of the block. An insulating layer is formed on the first side of the block; electrically conducting vias are formed in the insulating layer and coupled to the leads; a conducting layer is formed on the insulating layer and coupled to the conducting vias; and conducting paths are formed in the…
METHOD AND SYSTEM FOR MANAGING HARDWARE RESOURCES TO IMPLEMENT SYSTEM FUNCTIONS USING AN ADAPTIVE COMPUTING ARCHITECTURE
Granted: April 10, 2014
Application Number:
20140101410
An adaptable integrated circuit is disclosed having a plurality of heterogeneous computational elements coupled to an interconnection network. The interconnection network changes interconnections between the plurality of heterogeneous computational elements in response to configuration information. A first group of computational elements is allocated to form a first version of a functional unit to perform a first function by changing interconnections in the interconnection network…
3D MEMORY BASED ADDRESS GENERATOR
Granted: April 10, 2014
Application Number:
20140101409
Systems and methods are disclosed for reducing memory usage and increasing the throughput in variable-size Fast Fourier Transform (FFT) architectures. In particular, 3D symmetric virtual memory is disclosed to exploit the structure inherent in variable-size FFT computations. Data samples may be written to and read from the 3D symmetric virtual memory in a specific sequence of coordinates that exploits the structure inherent in variable-size FFT computations. Memory locations in the 3D…
METHOD FOR FINDING STARTING BIT OF REFERENCE FRAMES FOR AN ALTERNATING-PARITY REFERENCE CHANNEL
Granted: April 10, 2014
Application Number:
20140101350
The present invention discloses a method for locating the reference frames of the reference lane on the transmitting data bus. The present invention addresses this object by disclosing a method whereby the relationship between the size of the reference frame transmitted over the reference lane and the width of the data bus is such that the reference frame is bit-shifted automatically until it is aligned with the data bus.
