Adaptable Datapath for a Digital Processing System
Granted: August 29, 2013
Application Number:
20130227182
The present invention includes an adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with…
METHODS AND APPARATUS FOR AUTOMATIC FAULT DETECTION
Granted: August 29, 2013
Application Number:
20130226498
Techniques and mechanisms are provided to monitor signals including critical signals at the endpoints, or leaves, of one or more signal trees in an integrated circuit device. Sensors or layers of sensors may be configured in fault detection circuitry to monitor signals and compare them to static or dynamically varying values. The fault detection circuits may include OR-gate daisy chains that output a fault detection signal to control circuitry if any signal at a particular leaf deviates…
PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS
Granted: August 22, 2013
Application Number:
20130214815
In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
CONFIGURING A PROGRAMMABLE DEVICE USING HIGH-LEVEL LANGUAGE
Granted: August 15, 2013
Application Number:
20130212366
A method of configuring a programmable integrated circuit device uses a high-level language. The method includes compiling a plurality of virtual programmable devices from descriptions in the high-level language, describing a user configuration for the programmable integrated circuit device in the high-level language, parsing the user configuration using a programming processor, and selecting, as a result of that parsing, one of the compiled virtual programmable devices. That selected…
CONFIGURING A PROGRAMMABLE DEVICE USING HIGH-LEVEL LANGUAGE
Granted: August 15, 2013
Application Number:
20130212365
A method of preparing a programmable integrated circuit device for configuration using a high-level language includes compiling a plurality of virtual programmable devices from descriptions in said high-level language. The compiling includes compiling configurations of configurable routing resources from programmable resources of said programmable integrated circuit device, and compiling configurations of a plurality of complex function blocks from programmable resources of said…
Apparatus and Methods for Time-Multiplex Field-Programmable Gate Arrays
Granted: August 15, 2013
Application Number:
20130207688
A time-multiplexed field programmable gate array (TM-FPGA) includes programmable logic circuitry, programmable interconnect circuitry, and a plurality of context registers. A user's circuit can be mapped to the programmable logic circuitry, the programmable interconnect circuitry, and the plurality of context registers without the user's intervention in mapping the design.
FORWARD ERROR CORRECTION WITH CONFIGURABLE LATENCY
Granted: July 25, 2013
Application Number:
20130191702
A method of performing forward error correction with configurable latency, where a configurable latency algorithm evaluates a target Bit Error Rate (BER) against an actual BER and adjusts the size of a configurable buffer such that the target BER may be achieved when utilizing the smallest buffer size possible. When errors are corrected without the utilization of each of the configurable buffer locations, the algorithm reduces the size of the buffer by y buffer locations; the algorithm…
Methods And Apparatus For Motion Search Refinement In A SIMD Array Processor
Granted: July 18, 2013
Application Number:
20130182771
Various approaches for motion search refinement in a processing element are discussed. A k/2+L+k/2 register stores an expanded row of an L×L macro block. A k-tap filter horizontally interpolates over the expanded row generating horizontal interpolation results. A transpose storage unit stores the interpolated results generated by the k-tap filter for k/2+L+k/2 entries, wherein rows or columns of data may be read out of the transpose storage unit in pipelined register stages. A k-tap…
BIDIRECTIONAL WAVELENGTH CROSS CONNECT ARCHITECTURES USING WAVELENGTH ROUTING ELEMENTS
Granted: June 13, 2013
Application Number:
20130148923
Bidirectional wavelength cross connects include a plurality of ports, each configured to receive an input optical signals, each input optical signal having a plurality of spectral bands. At least one of the plurality of ports is disposed to simultaneously transmit an output optical signal having at least one of the spectral bands. A plurality of wavelength routing elements are configured to selectively route input optical signal spectral bands to output optical signals.
LOGIC DEVICE HAVING A COMPRESSED CONFIGURATION IMAGE STORED ON AN INTERNAL READ ONLY MEMORY
Granted: June 6, 2013
Application Number:
20130145074
Systems and methods for using an internal read only memory (ROM) to configure a logic device are described. The ROM and the logic device may be located on a single chip. The ROM may be adapted to store highly compressed configuration images and be non-reprogrammable. The logic device may be configured based on the compressed configuration image.
N-WELL/P-WELL STRAP STRUCTURES
Granted: June 6, 2013
Application Number:
20130140640
Embodiments of N-well or P-well strap structures are disclosed with lower requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.
METHODS AND APPARATUS FOR MATRIX DECOMPOSITIONS IN PROGRAMMABLE LOGIC DEVICES
Granted: June 6, 2013
Application Number:
20130140366
A processor is adapted for performing a QR-decomposition. The processor has a program memory, a program controller, connected to the program memory to receive program instructions, and at least one processing unit. The processing unit includes a CORDIC calculation block, and has a distributed memory structure, with separate memory blocks for storing respective parameter values.
2D PRODUCT CODE AND METHOD FOR DETECTING FALSE DECODING ERRORS
Granted: May 23, 2013
Application Number:
20130132794
The present invention discloses a method and apparatus for performing forward error correction with a multi-dimensional Bose Ray-Chaudhuri Hocquenghem (BCH) product code, and a method for detecting false decoding errors in frame-based data transmission systems.
CLOCK AND DATA RECOVERY CIRCUITRY WITH AUTO-SPEED NEGOTIATION AND OTHER POSSIBLE FEATURES
Granted: April 18, 2013
Application Number:
20130093482
An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the…
PROCESSOR TO MESSAGE-BASED NETWORK INTERFACE USING SPECULATIVE TECHNIQUES
Granted: March 7, 2013
Application Number:
20130061247
Methods and systems are provided for a message network interface unit (a message interface unit), coupled to a processor, that is used for allowing the processor to send messages to a hardware unit. Methods and systems are also provided for a message interface unit, coupled to a processor, that is used for allowing a processor to receive messages from a hardware unit. The message network interface unit described herein may allow for the implementation data-intensive, real time…
Manifold Array Processor
Granted: January 17, 2013
Application Number:
20130019082
An array processor includes processing elements arranged in to form a rectangular array. Inter-cluster communication paths are mutually exclusive. Due to the mutual exclusivity of the data paths, communications between the processing elements of each cluster may be combined in a single inter-cluster path, thus eliminating half the wiring required for the path. The length of the longest communication path is not directly determined by the overall dimension of the array, as in conventional…
FIELD PROGRAMMABLE GATE ARRAY WITH INTEGRATED APPLICATION SPECIFIC INTEGRATED CIRCUIT FABRIC
Granted: January 10, 2013
Application Number:
20130009666
A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA…
SOFTWARE-TO-HARDWARE COMPILER WITH SYMBOL SET INFERENCE ANALYSIS
Granted: January 10, 2013
Application Number:
20130014095
A software-to-hardware compiler is provided that generates hardware constructs in programmable logic resources. The programmable logic resources may be optimized in terms of being configured to make additional copies of regions on memory devices other than on the programmable logic resources (e.g., RAM). This facilitates multiple reads during a single clock cycle. Symbol set analysis is used to minimize the size of regions to allow for more efficient use of hardware resources.
METHOD AND SYSTEM FOR PARTIAL RECONFIGURATION SIMULATION
Granted: January 3, 2013
Application Number:
20130007687
Disclosed is a method of simulating partial reconfiguration of a programmable logic device (PLD). A wrapper module is incorporated into a logic description that may be implemented in a PLD. The wrapper module represents a first logic design. In response to receiving a parameter, the wrapper module changes to represent a second logic design. According to various embodiments, the logic description is a simulatable source file. The simulatable source file is a source file that is used by a…
Methods and Apparatus for Efficient Complex Long Multiplication and Covariance Matrix Implementation
Granted: January 3, 2013
Application Number:
20130007421
Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex…
