Methods and Apparatus for Efficient Complex Long Multiplication and Covariance Matrix Implementation
Granted: January 3, 2013
Application Number:
20130007421
Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex…
RECONFIGURABLE LOGIC BLOCK
Granted: January 3, 2013
Application Number:
20130007679
A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a…
METHOD AND SYSTEM FOR PARTIAL RECONFIGURATION SIMULATION
Granted: January 3, 2013
Application Number:
20130007687
Disclosed is a method of simulating partial reconfiguration of a programmable logic device (PLD). A wrapper module is incorporated into a logic description that may be implemented in a PLD. The wrapper module represents a first logic design. In response to receiving a parameter, the wrapper module changes to represent a second logic design. According to various embodiments, the logic description is a simulatable source file. The simulatable source file is a source file that is used by a…
Method and Apparatus For Performing Parallel Routing Using A Multi-Threaded Routing Procedure
Granted: January 3, 2013
Application Number:
20130007689
A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.
System Core for Transferring Data Between an External Device and Memory
Granted: January 3, 2013
Application Number:
20130007331
Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily…
Methods and Apparatus for Providing Bit-Reversal and Multicast Functions Utilizing DMA Controller
Granted: December 27, 2012
Application Number:
20120331185
Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal…
SYSTEMS AND METHODS FOR INTERFACING BETWEEN HARD LOGIC AND SOFT LOGIC IN A HYBRID INTEGRATED DEVICE
Granted: December 20, 2012
Application Number:
20120319730
Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that includes interconnects between hard logic and soft logic, which enable signals to be selectively routed between the inputs and outputs of hard logic blocks and soft logic modules. The interconnects allow for certain hard logic blocks to be bypassed in favor of soft logic functionality. Moreover,…
SEMICONDUCTOR TEST DATA ANALYSIS SYSTEM
Granted: December 13, 2012
Application Number:
20120316803
The invention concerns a system for processing semi-conductor test data relating to a plurality of dies formed by a manufacturing process on at least one silicon wafer, the system comprising: an input arranged to receive said semiconductor test data (202); one or more memories (226, 242) adapted to store a database comprising said semiconductor test data and a plurality of test data patterns, wherein each of said test data patterns is associated with a corresponding output data value…
MULTI-PROTOCOL MULTIPLE-DATA-RATE AUTO-SPEED NEGOTIATION ARCHITECTURE FOR A DEVICE
Granted: December 6, 2012
Application Number:
20120307878
An interface for use in a local device includes a transmitter portion programmably configurable to at least three data rates, a receiver portion programmably configurable to those at least three data rates, and an automatic speed negotiation module operatively connected to the transmitter portion and the receiver portion to configure the transmitter portion and the receiver portion for communication with a remote device at a single data rate that is a best available one of those at least…
STRICT-SENSE MINIMAL SPANNING SWITCH NON-BLOCKING ARCHITECTURE
Granted: November 15, 2012
Application Number:
20120287927
The present invention discloses an apparatus to implement a m=n Non-Blocking Minimal Spanning Switch, where n=the total number of data input signals and m=the total number of data output signals and m=the number of crossbar connections in each switch. Data is input to the switch as a plurality of frames, whereby each crossbar connection contains a framer which detects framing patterns in the data. Skewed data is re-aligned and buffered so that the data output by each crossbar connection…
DSP BLOCK WITH EMBEDDED FLOATING POINT STRUCTURES
Granted: November 15, 2012
Application Number:
20120290819
A specialized processing block includes a first floating-point arithmetic operator stage, a second floating-point arithmetic operator stage, and configurable interconnect within the specialized processing block for routing signals into and out of each of the first and second floating-point arithmetic operator stages. In some embodiments, the configurable interconnect may be configurable to route a plurality of block inputs to inputs of the first floating-point arithmetic operator stage,…
SYSTEMS AND METHODS FOR CONFIGURING AN SOPC WITHOUT A NEED TO USE AN EXTERNAL MEMORY
Granted: November 15, 2012
Application Number:
20120286821
Systems and techniques for configuration of a system on a programmable chip (SOPC) are described. By configuring the SOPC, during power-up, with a voltage input instead of with a flash memory or another non-volatile memory, the systems and techniques may save cost and board space.
SYSTEMS AND METHODS FOR PROVIDING USER-INITIATED LATCH UP TO DESTROY SRAM DATA
Granted: November 1, 2012
Application Number:
20120274350
Systems and methods are provided for destroying or erasing circuitry elements, data, or both, such as transistors, volatile keys, or fuse blocks, located in an integrated circuit device. An initiation signal may be provided to induce latch-up in a circuitry element in response to a user command, a tampering event, or both. As a result of the latch-up effect, the circuitry element, data, or both may be destroyed or erased.
METHOD AND APPARATUS FOR SECURING A PROGRAMMABLE DEVICE USING A KILL SWITCH
Granted: November 1, 2012
Application Number:
20120274351
A kill switch is provided that, when triggered, may cause the programmable logic device (PLD) to become at least partially reset, disabled, or both. The kill switch may be implemented as a fuse or a volatile battery-backed memory bit. When, for example, a security threat is detected, the switch may be blown, and a reconfiguration of the device initiated in order to zero or clear some or all of the memory and programmable logic of the PLD.
SYSTEMS AND METHODS FOR PREVENTING DATA REMANENCE IN MEMORY SYSTEMS
Granted: November 1, 2012
Application Number:
20120274353
Methods, circuits, and systems for preventing data remanence in memory systems are provided. Original data is stored in a first memory, which may be a static random access memory (SRAM). Data is additionally stored in a second memory. Data in the first memory is periodically inverted, preventing data remanence in the first memory. The data in the second memory is periodically inverted concurrently with the data in the first memory. The data in the second memory is used to keep track of…
HIGH-SPEED DIFFERENTIAL COMPARATOR CIRCUITRY WITH ACCURATELY ADJUSTABLE THRESHOLD
Granted: November 1, 2012
Application Number:
20120274359
A high-speed differential comparator circuit is provided with an accurately adjustable threshold voltage. Differential reference voltage signals are provided to control the threshold voltage of the comparator. The common mode voltage of the reference signals preferably tracks the common mode voltage of the differential high-speed serial data signal being processed by the comparator circuit.
SYSTEMS AND METHODS FOR SECURING A PROGRAMMABLE DEVICE AGAINST AN OVER-VOLTAGE ATTACK
Granted: November 1, 2012
Application Number:
20120275077
Systems and methods are disclosed for securing a programmable integrated circuit device against an over-voltage attack. Generally, programmable devices, such as FPGAs, contain volatile memory registers that may store sensitive information. To prevent tampering and/or reverse engineering of such a programmable device, an over-voltage detection circuit may be employed to disable the device and/or erase the sensitive information stored on the device when an over-voltage attack is suspected.…
METHOD OF ACCESSING STORED INFORMATION IN MULTI-FRAMED DATA TRANSMISSIONS
Granted: November 1, 2012
Application Number:
20120275462
The present invention discloses a method of accessing stored information in multi-framed data transmissions, comprising at least one control interface and at least one elastic store, wherein the control interface accesses the elastic store through a mailbox communications method. The control interface accesses the elastic store via the mailbox communications method, which comprises: (a) setting a address for a data location within said elastic store; (b) setting a request to read from,…
METHOD AND APPARATUS FOR SECURING PROGRAMMING DATA OF A PROGRAMMABLE DEVICE
Granted: November 1, 2012
Application Number:
20120278632
Configuration data for a programmable integrated circuit device is at least partially encrypted according to at least one encryption scheme. A plurality of key stores store a plurality of decryption keys for the at least one encryption scheme. Control circuitry identifies a required key from the at least partially encrypted configuration data and generates a key selection signal. Key selection circuitry responsive to the key selection signal reads the plurality of key stores and provides…
SYSTEMS AND METHODS FOR DETECTING AND MITIGATING PROGRAMMABLE LOGIC DEVICE TAMPERING
Granted: November 1, 2012
Application Number:
20120278906
Systems and methods are disclosed for preventing tampering of a programmable integrated circuit device. Generally, programmable devices, such as FPGAs, have two stages of operation; a configuration stage and a user mode stage. To prevent tampering and/or reverse engineering of a programmable device, various anti-tampering techniques may be employed during either stage of operation to disable the device and/or erase sensitive information stored on the device once tampering is suspected.…
