BIT ERROR RATE CHECKER RECEIVING SERIAL DATA SIGNAL FROM AN EYE VIEWER
Granted: March 22, 2012
Application Number:
20120072785
An IC that includes an eye viewer and a BER checker coupled to the eye viewer, where the BER checker receives a serial data signal from the eye viewer, is provided. In one implementation, the BER checker receives the serial data signal from the eye viewer without the serial data signal passing through a deserializer. In one implementation, the BER checker compares the serial data signal against a reference data signal to determine the BER for the serial data signal. In one…
Techniques for Varying a Periodic Signal Based on Changes in a Data Rate
Granted: March 15, 2012
Application Number:
20120063556
A circuit includes a phase detection circuit, a phase adjustment circuit, and a sampler circuit. The phase detection circuit compares a phase of a first periodic signal to a phase of a second periodic signal to generate a control signal. The phase adjustment circuit causes the phase of the second periodic signal and a phase of a third periodic signal to vary based on a variation in the control signal. The sampler circuit samples a data signal to generate a sampled data signal in response…
LANE-TO-LANE SKEW REDUCTION IN MULTI-CHANNEL, HIGH-SPEED, TRANSCEIVER CIRCUITRY
Granted: March 15, 2012
Application Number:
20120063539
Controllable delay circuitry is included in each channel of multi-channel, high-speed, serial transmitter and/or receiver circuitry to compensate for or to at least help compensate for possible skew (different signal propagation time) between the various channels. In systems employing CDR circuitry, the delay circuitry may be at least partly controlled by a signal derived from the CDR circuitry to make the amount of delay effected by the delay circuitry at least partly responsive to…
Methods and Apparatus For Single Testing Stimulus
Granted: March 8, 2012
Application Number:
20120060140
Methods and apparatus useful for improving the performance of testing and diagnostic operations on user circuit designs potentially across multiple phases of the development lifecycle and across multiple implementation technologies are described. As one example, a single testing and diagnostic stimulus source can variously provide test pattern data to different potential instantiations of the user circuit design by supporting and selectively utilizing a number of DUT-facing communication…
CALCULATION OF TRIGONOMETRIC FUNCTIONS IN AN INTEGRATED CIRCUIT DEVICE
Granted: March 1, 2012
Application Number:
20120054256
Circuitry for computing a tangent function of an input value includes first look-up table circuitry that stores pre-calculated tangent values of a limited number of sample values, circuitry for inputting bits of the input value of most significance as inputs to the first look-up table circuitry to look up one of the pre-calculated tangent values as a first intermediate tangent value, circuitry for calculating a second intermediate tangent value from one or more ranges of remaining bits…
CALCULATION OF TRIGONOMETRIC FUNCTIONS IN AN INTEGRATED CIRCUIT DEVICE
Granted: March 1, 2012
Application Number:
20120054254
Circuitry for computing a trigonometric function of an input includes circuitry for relating the input to another value to generate an intermediate value, circuitry for selecting one of the input and the intermediate value as a trigonometric input value, circuitry for determining respective initial values of a plurality of trigonometric functions for the trigonometric input value, and circuitry for deriving, based at least in part on a trigonometric identity, a final value of the first…
N-WELL/P-WELL STRAP STRUCTURES
Granted: February 9, 2012
Application Number:
20120032276
Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.
METHODS AND APPARATUS FOR MATRIX DECOMPOSITIONS IN PROGRAMMABLE LOGIC DEVICES
Granted: January 12, 2012
Application Number:
20120011344
A processor is adapted for performing a QR-decomposition. The processor has a program memory, a program controller, connected to the program memory to receive program instructions, and at least one processing unit. The processing unit includes a CORDIC calculation block, and has a distributed memory structure, with separate memory blocks for storing respective parameter values.
CALCULATION OF TRIGONOMETRIC FUNCTIONS IN AN INTEGRATED CIRCUIT DEVICE
Granted: December 29, 2011
Application Number:
20110320513
Circuitry for computing a trigonometric function of an input includes circuitry for relating the input to another value to generate an intermediate value, circuitry for selecting one of the input and the intermediate value as a trigonometric input value, circuitry for determining respective initial values of a plurality of trigonometric functions for the trigonometric input value, and circuitry for deriving, based at least in part on a trigonometric identity, a final value of the first…
PROCESSORS OPERABLE TO ALLOW FLEXIBLE INSTRUCTION ALIGNMENT
Granted: December 22, 2011
Application Number:
20110314265
Methods and apparatus are provided for optimizing a processor core. Common processor subcircuitry is used to perform calculations for various types of instructions, including branch and non-branch instructions. Increasing the commonality of calculations across different instruction types allows branch instructions to jump to byte aligned memory address even if supported instructions are multi-byte or word aligned.
Methods and Apparatus for Providing Bit-Reversal and Multicast Functions Utilizing DMA Controller
Granted: December 8, 2011
Application Number:
20110302333
Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal…
Input/Output Interface For Periodic Signals
Granted: December 1, 2011
Application Number:
20110292950
A first periodic signal generation circuit generates first periodic output signals. A second periodic signal generation circuit generates second periodic output signals. A first multiplexer circuit receives the first and the second periodic output signals. An interface circuit coupled to external pins generates a third periodic output signal based on a periodic signal selected by the first multiplexer circuit. A second multiplexer circuit receives the third periodic output signal at an…
LOW-POWER ROUTING MULTIPLEXERS
Granted: November 3, 2011
Application Number:
20110267106
Low-power routing multiplexers that reduce static and dynamic power consumption are provided. A variety of different techniques are used to reduce power consumption of the routing multiplexers without significantly increasing their size. For example, power consumption of the routing multiplexers may be reduced by reducing short-circuit currents, reducing leakage currents, limiting voltage swing, and recycling charge within the multiplexer. Multiple power reduction techniques may be…
MULTIPLE DATA RATE MEMORY INTERFACE ARCHITECTURE
Granted: October 27, 2011
Application Number:
20110260751
The present invention provides a DQS bus for implementing high speed multiple-data-rate interface architectures in programmable logic devices. The DQS bus has a balanced tree structure between at least one data strobe circuit and a plurality of I/O register blocks.
SOLVING LINEAR MATRICES IN AN INTEGRATED CIRCUIT DEVICE
Granted: September 29, 2011
Application Number:
20110238720
Circuitry for solving linear matrix equations involving a resultant matrix, an unknown matrix and a product matrix that is a product of the resultant matrix and the unknown matrix includes matrix decomposition circuitry for triangulating an input matrix to create a resultant matrix having a plurality of resultant matrix elements on a diagonal, and having a further plurality of resultant matrix elements arranged in columns below the resultant matrix elements on the diagonal. The matrix…
LOOK UP TABLE STRUCTURE SUPPORTING QUATERNARY ADDERS
Granted: September 29, 2011
Application Number:
20110238718
A lookup table structure having multiple lookup tables is configured to include a quaternary adder. In particular examples, an adaptive logic module (ALM) including a fracturable lookup table (LUT) is configured to include a quaternary (4-1) adder. In some examples, only an XOR gate, an AND gate, two single bit 2-1 multiplexers, and minor connectivity changes to a LUT structure supporting a ternary (3-1) adder are needed to support 4-1 adders. Binary (2-1) and ternary adders are still…
SIGNAL LOSS DETECTOR FOR HIGH-SPEED SERIAL INTERFACE OF A PROGRAMMABLE LOGIC DEVICE
Granted: September 29, 2011
Application Number:
20110235756
A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss…
PROGRAMMABLE HIGH-SPEED INTERFACE
Granted: September 22, 2011
Application Number:
20110227606
Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to…
Efficient Complex Multiplication and Fast Fourier Transform (FFT) Implementation on the ManArray Architecture
Granted: September 15, 2011
Application Number:
20110225224
Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline…
Methods and Apparatus for Providing Bit-Reversal and Multicast Functions Utilizing DMA Controller
Granted: September 15, 2011
Application Number:
20110225392
Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal…
