DATA PROCESSING METHOD AND DEVICE
Granted: October 25, 2012
Application Number:
20120271801
The invention concerns a method of processing data to provide output data based on a group of data samples having a time stamp falling within at least one rolling time period, the method comprising: receiving a new data sample (DN) and associating said new data sample with a first time stamp; updating said output data corresponding to a first rolling time period to be based on said group of data samples including said new data sample; programming a first callback based on said first time…
PROGRAMMABLE CONTROL BLOCK FOR DUAL PORT SRAM APPLICATION
Granted: October 18, 2012
Application Number:
20120263000
A dual-port static random access memory (SRAM) includes a multitude of programmable delay elements disposed along the paths of a number signals used to carry out read, write or read-then-write operations. At least one of the programmable delay elements controls the timing margin between a pair of clock signals that trigger a read/write enable signal. A second programmable delay element coarsely adjusts the delay of a first signal associated with a dummy bitline. A third programmable…
Techniques for Reducing Duty Cycle Distortion in Periodic Signals
Granted: October 11, 2012
Application Number:
20120256670
A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of…
SYSTEMS AND METHODS FOR USING MEMORY COMMANDS
Granted: October 11, 2012
Application Number:
20120260032
Systems and methods for using memory commands are described. The systems include a memory controller. The memory controller receives a plurality of user transactions. The memory controller converts each user transaction into one or more row and column memory commands. The memory controller reorders the memory commands associated with the plurality of user transactions before sending the memory commands to a memory device.
INTEGRATED OPTICAL-ELECTRONIC INTERFACE IN PROGRAMMABLE INTEGRATED CIRCUIT DEVICE
Granted: October 4, 2012
Application Number:
20120251116
Systems that provide integrated circuit device circuitry having an integrated optical-electronic interface for high-speed off-device communications are provided. An optical-electronic interface may be incorporated into an integrated circuit device, freeing up some or all of the electrical I/O pins of the integrated circuit device. Transceiver I/O channels may be provided on an integrated circuit device that can be switched between electrical and optical transceiver I/O channels.
SYSTEMS INCLUDING AN I/O STACK AND METHODS FOR FABRICATING SUCH SYSTEMS
Granted: September 13, 2012
Application Number:
20120228760
Systems including an input/output (I/O) stack and methods for fabricating such systems are described. In one implementation, the methods include stacking an I/O die including I/O elements and excluding a logic element. Also in one implementation, the methods further include stacking an integrated circuit die with respect to the I/O die. The integrated circuit includes logic elements and excludes an I/O element. The separation of the I/O die from the integrated circuit die provides…
Techniques For Measuring Voltages in a Circuit
Granted: September 13, 2012
Application Number:
20120229169
A circuit includes a comparator, a programmable current source, and a control circuit. The comparator is operable to compare an internal supply voltage of the circuit to a reference voltage. The programmable current source is operable to supply a first current for the reference voltage. The control circuit is operable to control the first current through the programmable current source based on an output signal of the comparator.
DOUBLE-CLOCKED SPECIALIZED PROCESSING BLOCK IN AN INTEGRATED CIRCUIT DEVICE
Granted: September 13, 2012
Application Number:
20120233230
Circuitry for increasing the precision of multipliers by a desired factor while limiting the increase in arithmetic complexity of the multiplier to that factor can be provided in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device (PLD). The smaller increase in arithmetic complexity, so that the increase is proportional to the increase in precision, rather than to the square of the increase in precision, is achieved…
Method and Apparatus for Placement and Routing of Partial Reconfiguration Modules
Granted: September 6, 2012
Application Number:
20120227026
A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed.
PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS
Granted: August 30, 2012
Application Number:
20120217998
In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
APPARATUS AND METHODS FOR COMMUNICATING WITH PROGRAMMABLE DEVICES
Granted: August 23, 2012
Application Number:
20120213017
A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.
Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response
Granted: July 5, 2012
Application Number:
20120173849
Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in…
MULTIPLE DATA RATE INTERFACE ARCHITECTURE
Granted: June 14, 2012
Application Number:
20120146700
Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.
METHOD OF MULTIPLE LANE DISTRIBUTION (MLD) DESKEW
Granted: June 14, 2012
Application Number:
20120147905
The present invention discloses a method of detecting and correcting skew across a plurality of transmitting lanes. Through the use of an N framer system, including a frame start signal and a frame synchronization signal, skew can be detected and corrected by writing data from a plurality of framers into offsetting bit locations of a plurality of buffers. The present invention also provides a method of transmitting data in a multiple lane distribution (MLD) transmission system.
Methods And Apparatus For Independent Processor Node Operations In A SIMD Array Processor
Granted: May 24, 2012
Application Number:
20120131310
A control processor is used for fetching and distributing single instruction multiple data (SIMD) instructions to a plurality of processing elements (PEs). One of the SIMD instructions is a thread start (Tstart) instruction, which causes the control processor to pause its instruction fetching. A local PE instruction memory (PE Imem) is associated with each PE and contains local PE instructions for execution on the local PE. Local PE Imem fetch, decode, and execute logic are associated…
Method and Apparatus for Performing Parallel Routing Using a Multi-Threaded Routing Procedure
Granted: May 24, 2012
Application Number:
20120131535
A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.
System Core for Transferring Data Between an External Device and Memory
Granted: May 17, 2012
Application Number:
20120124335
Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily…
WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES
Granted: May 3, 2012
Application Number:
20120106264
Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS…
Method and Apparatus for Performing Memory Interface Calibration
Granted: May 3, 2012
Application Number:
20120110400
A universal memory interface on an integrated circuit includes an external memory interface unit operable to perform data rate conversion for a data signal between a first rate associated with the integrated circuit and a second rate associated with a memory system. The universal memory interface also includes a sequencer unit operable to calibrate at least one of a delay for the data signal and a delay for a strobe for the data signal by executing a calibration procedure instruction.
Power Management of Components Having Clock Processing Circuits
Granted: March 22, 2012
Application Number:
20120072756
A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to the clock processing circuit. A frequency of a clock signal supplied to the clock processing circuit is changed based on operating characteristics of a voltage regulator module (VRM) or power supply unit so as to maintain acceptable operating parameters of the power supply unit during a change…
