Transceiver system with reduced latency uncertainty
Granted: June 25, 2009
Application Number:
20090161738
A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the…
Methods of reducing power in programmable devices using low voltage swing for routing signals
Granted: June 11, 2009
Application Number:
20090146688
Reduced voltage swing signal path circuitry is provided that lowers the internal signaling power consumption of the interconnection resources of a programmable logic device. The reduced voltage swing signal path circuitry includes a reversed routing driver circuitry to limit the voltage range of the output signal of the driver circuitry.
ADAPTIVE EQUALIZATION METHODS AND APPARATUS
Granted: June 4, 2009
Application Number:
20090141787
A system includes a programmable transmitter device (e.g., a PLD) connected to a programmable receiver device (e.g., another PLD) via a transmission medium for transmitting a high-speed data signal from the transmitter to the receiver. During a test mode of operation a low-speed communication link between the transmitter and receiver allows those devices to work together to transmit test signals having known characteristics from the transmitter to the receiver via the transmission…
SYSTEMS AND METHODS FOR REDUCING STATIC AND TOTAL POWER CONSUMPTION
Granted: May 28, 2009
Application Number:
20090138696
A method and system for reducing power consumption in a programmable logic device (PLD) is provided. The power consumption may be reduced by preferably continually considering power consumption as a factor in circuit design during the technology mapping, routing, and period following routing of the programmable logic device.
Methods and Apparatus for Transforming, Loading, and Executing Super-Set Instructions
Granted: May 7, 2009
Application Number:
20090119489
Techniques are described for loading decoded instructions and super-set instructions in a memory for later access. For loading a decoded instruction, the decoded instruction is a transformed form of an original instruction that was stored in the program memory. The transformation is from an encoded assembly level format to a binary machine level format. In one technique, the transformation mechanism is invoked by a transform and load instruction that causes an instruction retrieved from…
SATURATION AND ROUNDING IN MULTIPLY-ACCUMULATE BLOCKS
Granted: April 16, 2009
Application Number:
20090100122
Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuits implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.
Methods and Apparatus for Single Stage Galois Field Operations
Granted: March 5, 2009
Application Number:
20090063606
Techniques for single function stage Galois field (GF) computations are described. The new single function stage GF multiplication requires only m-bits per internal logic stage, a savings of m?1 bits per logic stage that do not have to be accounted for as compared with a previous two function stage approach. Also, a common design CF multiplication cell is described that may be suitably used to construct an m-by-m GF multiplication array for the calculation of GF[2m]/g[x]. In addition,…
Field programmable gate array with integrated application specific integrated circuit fabric
Granted: February 26, 2009
Application Number:
20090051387
A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA…
Programmable Control Block For Dual Port SRAM Application
Granted: February 12, 2009
Application Number:
20090040846
A dual-port static random access memory (SRAM) includes a multitude of programmable delay elements disposed along the paths of a number signals used to carry out read, write or read-then-write operations. At least one of the programmable delay elements controls the timing margin between a pair of clock signals that trigger a read/write enable signal. A second programmable delay element coarsely adjusts the delay of a first signal associated with a dummy bitline. A third programmable…
Phase shift circuit with lower intrinsic delay
Granted: January 29, 2009
Application Number:
20090027098
A phase shift circuit that includes two, rather than four, delay chains and corresponding selectors is described. This provides a significant area savings and reduces the intrinsic delay of the phase shift circuit, which is particularly beneficial for embodiments in which there is no intrinsic delay matching. In one specific implementation, the phase shift circuit includes a first delay circuit and a matching delay circuit. The first delay circuit provides a first delay that includes a…
EFFICIENT DELAY ELEMENTS
Granted: January 15, 2009
Application Number:
20090015308
Circuits, methods, and apparatus for delaying signals in a power and area efficient manner are provided. A gating element within a stage of a programmable delay element suppresses an operation of other stages of the delay element. A programmable delay has components with differing delays that may be combined to give flexibility in choices for delay increments while minimizing the area of the delay element. A delay element is shared between different signal paths, for example, to reduce…
Methods and Apparatus for a Bit Rake Instruction
Granted: January 15, 2009
Application Number:
20090019269
Techniques for performing a bit rake instruction in a programmable processor. The bit rake instruction extracts an arbitrary pattern of bits from a source register, based on a mask provided in another register, and packs and right justifies the bits into a target register. The bit rake instruction allows any set of bits from the source register to be packed together.
SIGNAL LOSS DETECTOR FOR HIGH-SPEED SERIAL INTERFACE OF A PROGRAMMABLE LOGIC DEVICE
Granted: January 8, 2009
Application Number:
20090011716
A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss…
TECHNIQUES FOR OPTIMIZING DESIGN OF A HARD INTELLECTUAL PROPERTY BLOCK FOR DATA TRANSMISSION
Granted: December 4, 2008
Application Number:
20080297192
Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error…
Techniques for Providing Calibrated On-Chip Termination Impedance
Granted: December 4, 2008
Application Number:
20080297193
Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to…
Efficient Complex Multiplication and Fast Fourier Transform (FFT) Implementation on the ManArray Architecture
Granted: December 4, 2008
Application Number:
20080301414
Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline…
PROGRAMMABLE LOGIC DEVICE HAVING LOGIC MODULES WITH IMPROVED REGISTER CAPABILITIES
Granted: November 27, 2008
Application Number:
20080290897
A PLD that has more flip flops per logic module by providing more registered outputs than combinational outputs; and/or a combinational output that can drive more than one register is disclosed. The PLD includes a plurality of logic array blocks arranged in an array and a plurality of inter-logic array block lines interconnecting the logic array blocks of the array. At least one of the logic array blocks includes at least one logic module that includes a first combinational element…
PROGRAMMABLE LOGIC DEVICE HAVING COMPLEX LOGIC BLOCKS WITH IMPROVED LOGIC CELL FUNCTIONALITY
Granted: November 27, 2008
Application Number:
20080290898
A CLB-based PLD with logic cells having improved logic, register, arithmetic, logic packing and timing functions and capabilities is disclosed. The CLBs of the PLD are arranged in rows and columns of an array and are interconnect by a plurality of interconnect lines. Each of the plurality of CLBs has a first slice of logic cells and a second slice of logic cells arranged in a first column and a second column. First and second carry chains are provided between each of the logic cells of…
READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA
Granted: November 27, 2008
Application Number:
20080291758
Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between…
SPREAD SPECTRUM CLOCK SIGNAL GENERATION SYSTEM AND METHOD
Granted: November 6, 2008
Application Number:
20080273574
A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a digital representation of a timing for each edge to impart spread spectrum modulation to the clock signal. A programmable modulator is provided that generates digital values representing edge positions for edges of a clock signal based on at least one of a time-varying period value and a…
