CLOCK SIGNAL NETWORKS FOR STRUCTURED ASIC DEVICES
Granted: October 23, 2008
Application Number:
20080258772
Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock…
Flexible RAM Clock Enable
Granted: October 16, 2008
Application Number:
20080253220
A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block.
Phase Frequency Detectors Generating Minimum Pulse Widths
Granted: October 9, 2008
Application Number:
20080246516
A phase frequency detector compares a reference clock signal to a feedback clock signal to generate pulses in one or more output signals. The one or more output signals have a minimum pulse width. The phase frequency detector has a temperature sensing circuit. The phase frequency detector adjusts the minimum pulse width of the one or more output signals using the temperature sensing circuit to compensate for variations in the temperature of the phase frequency detector.
Staggered logic array block architecture
Granted: September 25, 2008
Application Number:
20080231317
A staggered logic array block (LAB) architecture can be provided. An integrated circuit (IC) device can include a first group of LABs substantially aligned with each other, and a second group of LABs substantially aligned with each other and coupled to the first group of LABs by a plurality of horizontal and vertical conductors. The first group of LABs can be substantially offset from the second group of LABs in the IC layout. In an embodiment of the invention, the first and second…
Methods and Apparatus for Dynamic Instruction Controlled Reconfigurable Register File
Granted: September 25, 2008
Application Number:
20080235496
A scalable reconfigurable register file (SRRF) containing multiple register files, read and write multiplexer complexes, and a control unit operating in response to instructions is described. Multiple address configurations of the register files are supported by each instruction and different configurations are operable simultaneously during a single instruction execution. For example, with separate files of the size 32×32 supported configurations of 128×32 bit s, 64x64 bit s and…
PROTOCOL-AGNOSTIC AUTOMATIC RATE NEGOTIATION FOR HIGH-SPEED SERIAL INTERFACE IN A PROGRAMMABLE LOGIC DEVICE
Granted: September 18, 2008
Application Number:
20080225933
Automatic rate negotiation logic for a high speed serial interface in a programmable logic device determines whether multiple occurrences of a single-bit transition (i.e., a data transition from “0” to “1” to “0” or from “1” to “0” to “1”) occur within a predetermined time interval on a data channel of a high-speed serial interface. The interval preferably is selected such that multiple occurrences of a single-bit transition mean that the data channel is operating…
PROGRAMMABLE LOGIC DEVICE HAVING REDUNDANCY WITH LOGIC ELEMENT GRANULARITY
Granted: September 11, 2008
Application Number:
20080218197
A PLD having logic element row granularity redundancy is disclosed. The PLD includes a plurality of LABs arranged in an array and a plurality of horizontal and vertical inter-LAB lines interconnecting the LABs of the array. Each of the LABs further includes a predetermined number of logic elements and redundancy circuitry to replace a defective logic element with a non-defective logic element among the predetermined logic elements by shifting programming data intended to for the…
PROGRAMMABLE LOGIC DEVICE HAVING LOGIC ARRAY BLOCK INTERCONNECT LINES THAT CAN INTERCONNECT LOGIC ELEMENTS IN DIFFERENT LOGIC BLOCKS
Granted: September 11, 2008
Application Number:
20080218208
A PLD with LAB interconnect lines that span adjacent LABs in the array and that have the ability to interconnect two logic elements in the different LABs. The PLD includes a plurality of LABs arranged in an array and a plurality of inter-LAB lines interconnecting the LABs of the array. Each of the LABs include a predetermined number of logic elements, one or more control signals distributed among the predetermined number of logic elements in the LAB, and LAB lines spanning between logic…
Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response
Granted: September 11, 2008
Application Number:
20080222333
Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in…
Performance Visualization of Delay in Circuit Design
Granted: September 4, 2008
Application Number:
20080216034
Methods are provided for presenting delay characteristics of a circuit design. The methods acquire routing delay data and logic delay data for each of a number of paths within the circuit design. In one method, a scatterplot of the routing delay data versus the logic delay data for each of the paths is generated and rendered. In another method, the paths are specified as being associated with modules within the circuit design. In this method, a histogram plot of the paths within each…
APPARATUS AND METHOD FOR A PROGRAMMABLE LOGIC DEVICE HAVING IMPROVED LOOK UP TABLES
Granted: August 21, 2008
Application Number:
20080197879
A programmable logic device including a plurality of logic elements organized in an array. Each of the logic elements includes an N-stage Look Up Table structure having 2N configuration bit inputs and a Look Up Table output. The first stage of the Look Up Table includes 2N tri-state buffers coupled to receive the 2N configuration bit inputs respectively. A decoder, configured from logic gates, is coupled to receive to one or more Look Up Table select signals and to generate a set of…
WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES
Granted: August 21, 2008
Application Number:
20080201597
Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS…
Reference clock receiver compliant with LVPECL, LVDS and PCI-Express supporting both AC coupling and DC coupling
Granted: August 21, 2008
Application Number:
20080197906
A reference clock receiver structure according to the invention is provided. The structure preferably includes an input buffer that is formed from a PMOS differentiated pair of transistors and a first supply voltage. The PMOS differential pair receives a pair of differential inputs, and produces a pair of differential outputs. The structure also includes a level shifter that is coupled to receive the pair of differential outputs from the input buffer to provide gain to the pair of…
PROGRAMMABLE HIGH-SPEED INTERFACE
Granted: August 7, 2008
Application Number:
20080186056
Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to…
Bidirectional Wavelength Cross Connect Architectures Using Wavelength Routing Elements
Granted: July 10, 2008
Application Number:
20080166123
Bidirectional wavelength cross connects include a plurality of ports, each configured to receive an input optical signals, each input optical signal having a plurality of spectral bands. At least one of the plurality of ports is disposed to simultaneously transmit an output optical signal having at least one of the spectral bands. A plurality of wavelength routing elements are configured to selectively route input optical signal spectral bands to output optical signals.
APPARATUS AND METHODS FOR COMMUNICATING WITH PROGRAMMABLE LOGIC DEVICES
Granted: July 3, 2008
Application Number:
20080157813
A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.
APPARATUS AND METHODS FOR COMMUNICATING WITH PROGRAMMABLE LOGIC DEVICES
Granted: June 19, 2008
Application Number:
20080143378
A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.
APPARATUS AND METHODS FOR IMPORTING HARDWARE DESIGN AND GENERATING CIRCUIT INTERFACES
Granted: June 19, 2008
Application Number:
20080147359
A system for designing a circuit, which includes a module, uses a computer. A user may program or adapt the computer to perform computer-aided design functions. The computer obtains a description of the module from the user. The computer parses the description of the module to identify a port of the module, and to obtain information about the port. The computer presents to the user the information that it has obtained about the port.
Dedicated crossbar and barrel shifter block on programmable logic resources
Granted: June 12, 2008
Application Number:
20080136449
A dedicated hardware block is provided for implementing crossbars and/or barrel shifters in programmable logic resources. Crossbar and/or barrel shifter circuitry may replace one or more rows, one or more columns, one or more rectangles, or any combination thereof of programmable logic regions on a programmable logic resource. The functionality of the crossbar and/or barrel shifter circuitry can further be improved by implementing time-multiplexing.
LARGE MULTIPLIER FOR PROGRAMMABLE LOGIC DEVICE
Granted: June 5, 2008
Application Number:
20080133627
A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another…
