Automatic adjustment of optimization effort in configuring programmable devices
Granted: October 5, 2006
Application Number:
20060225021
User designs are assigned to a category for each design goal associated with the user design. Each category represents the difficulty of satisfying a design goal. Optimization phases are tailored to different combinations of categories and are selected according to the categories assigned to the user design. A ranking of the relative difficulty of the design goals is determined from the categories associated with the user design. Parameters of an optimization phase can be modified in…
Programmable high speed interface
Granted: October 5, 2006
Application Number:
20060220703
Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to…
I/O circuitry shared between processor and programmable logic portions of an integrated circuit
Granted: August 24, 2006
Application Number:
20060186917
The present invention provides circuitry and methods for sharing I/O pins between a programmable logic portion and an embedded processor portion of a chip. The circuits in the programmable logic portion and the embedded processor portion can access data signals from and send data signals to the same I/O pins. The data signals are multiplexed to control access to the shared I/O pins. The multiplexers may be controlled by a control signal that determines when particular I/O pins are…
Method for incorporating pattern dependent effects in circuit simulations
Granted: August 24, 2006
Application Number:
20060190854
Methods, software, and apparatus for providing a netlist for simulation that includes one or more parameters that are determined by one or more pattern dependent effects. One particular embodiment of the present invention receives a layout of a circuit including one or more MOSFET transistors. For one or more of the MOSFET transistors, spacing between transistors is measured using the received layout and a pattern dependent parameter is determined. This parameter modifies the length of…
Methods and apparatus for implementing parameterizable processors and peripherals
Granted: August 24, 2006
Application Number:
20060190907
Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically generated, allowing extensive parameterization of various modules. Dynamic generation also allows the delivery of device driver logic onto a…
Glitch free reset circuit
Granted: July 6, 2006
Application Number:
20060145727
An apparatus for compensating for glitch occurrence in a reset signal that is applied in an integrated circuit, includes: a logic stage capable to process an incoming signal and a delayed incoming signal that is a delayed version of the incoming signal, the logic stage capable to generate an output signal so that when the incoming signal and the delayed incoming signal are in the same state, the output signal will be in the same state. An apparatus for compensating for glitch occurrence…
Merged logic element routing multiplexer
Granted: June 22, 2006
Application Number:
20060132176
A merged logic element routing multiplexer circuit includes one or more inputs coupled to the logic element (LE) output, one or more tri-stated circuits coupled to the corresponding one or more inputs, wherein the tri-stated circuits are controlled by a set of programmable select signals, and an output port coupled to the inter logic array block (LAB) routing wire, where the output port is connected to outputs of the tri-stated circuits through a buffer circuit.
Techniques for optimizing design of a hard intellectual property block for data transmission
Granted: June 15, 2006
Application Number:
20060125517
Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error…
Techniques for combining volatile and non-volatile programmable logic on an integrated circuit
Granted: June 8, 2006
Application Number:
20060119384
Techniques for combining volatile and non-volatile programmable logic into one integrated circuit (IC) are provided. An IC is segregated into two portions. A first block of programmable logic is configured by bits stored in on-chip non-volatile memory. A second block of programmable logic is configured by bits stored in off-chip memory. The function of IO banks on the IC is multiplexed between the two logic blocks of the IC. The programmable logic in the first block can be configured and…
Techniques for implementing hardwired decoders in differential input circuits
Granted: June 8, 2006
Application Number:
20060119386
Techniques are provided for improving signal timing characteristics of differential input/output (IO) circuits on programmable logic integrated circuits. A differential buffer receives differential signals applied to differential input pins. The output signals of the differential buffer are routed to two hard IO decoder blocks that are located in two adjacent rows/columns of programmable logic elements. Each IO decoder block has a data-in register that receives output signals of the…
Output reporting techniques for hard intellectual property blocks
Granted: June 1, 2006
Application Number:
20060114022
Techniques for reducing the frequency of an output signal from a hard intellectual property (HIP) block on an integrated circuit are provided. By reducing the frequency of the output signal, circuit blocks in the integrated circuit that operate at a lower frequency than the HIP block are able to capture the output signal. A plurality of serially coupled flip-flops store values of an HIP output signal during each period of the output signal. Logic circuitry then generates a lower…
Analog-to-digital converter for programmable logic
Granted: March 30, 2006
Application Number:
20060066464
Digital-to-analog and analog-to-digital conversion are implemented in or using programmable logic. The DAC and ADC circuits may be hardwired in a programmable logic integrated circuit or may be implemented using an intellectual property (IP) core. The IP core would be a series of bits to configure the logic cells and other programmable logic of an integrated circuit to include one or more DACs or ADC, or both on the same integrated circuit. The DAC may be a sigma-delta-modulator-based…
Compact SCR device and method for integrated circuits
Granted: March 16, 2006
Application Number:
20060054974
A semiconductor device and method for electrostatic discharge protection. The semiconductor device includes a first semiconductor controlled rectifier and a second semiconductor controlled rectifier. The first semiconductor controlled rectifier includes a first semiconductor region and a second semiconductor region, and the second semiconductor controlled rectifier includes the first semiconductor region and the second semiconductor region. The first semiconductor region is associated…
Techniques for trimming drive current in output drivers
Granted: February 16, 2006
Application Number:
20060033532
Techniques are provided for trimming drive current in output drivers to compensate for process variations, model inaccuracies, and/or an off-target process. The actual output drive current is measured on the integrated circuit (IC) at wafer sort or during a final test. Based on the measured output drive current, the total transistor width that is required in the output driver to meet an I/O standard is calculated. A control block controls trimming transistors that are coupled in parallel…
Methods and apparatus for implementing parameterizable processors and peripherals
Granted: February 16, 2006
Application Number:
20060036988
Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically generated, allowing extensive parameterization of various modules. Dynamic generation also allows the delivery of device driver logic onto a…
ENHANCED PASSGATE STRUCTURES FOR REDUCING LEAKAGE CURRENT
Granted: February 9, 2006
Application Number:
20060028240
Enhanced passgate structures for use in low-voltage systems are presented in which the operational speed of the passgate structures is maximized, while minimizing leakage current when the structure is turned “OFF.” In one arrangement, the VT of the pass-gate structures is increased relative to the VT of other transistors fabricated according to a particular process dimension. In addition, a passgate activation voltage is applied to the passgate structures such that the passgate…
Fracturable lookup table and logic element
Granted: January 26, 2006
Application Number:
20060017460
A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls…
Redundancy structures and methods in a programmable logic device
Granted: December 1, 2005
Application Number:
20050264318
An embodiment of the present invention provides a programmable logic device (“PLD”) including a redundancy architecture adapted to selective route signals via first or second staggered vertical lines. Other embodiments provide configuration logic and programs for determining routing selections. Other embodiments provide proximate grouping of vertical lines driven from a same row. Other embodiments provide definition of spare row locations once defective row locations are known.
Optimized processors and instruction alignment
Granted: October 6, 2005
Application Number:
20050223198
Methods and apparatus are provided for optimizing a processor core. Common processor subcircuitry is used to perform calculations for various types of instructions, including branch and non-branch instructions. Increasing the commonality of calculations across different instruction types allows branch instructions to jump to byte aligned memory address even if supported instructions are multi-byte or word aligned.
Dynamic RAM storage techniques
Granted: September 15, 2005
Application Number:
20050201141
Dynamic RAM (DRAM) cells are provided. Data can be read from a DRAM cell without draining the stored charge stored in the cell. During a read cycle, current flows between a Read Bit line and a supply voltage, and charge is not drained directly from the DRAM storage node. Each DRAM cell has a small number of transistors. The DRAM cell can be used to store configuration data on a programmable integrated circuits (IC). Pass gates are used on programmable ICs to drive signals across the…
