Automatic test component generation and inclusion into simulation testbench
Granted: October 4, 2007
Application Number:
20070234247
Methods and apparatus are provided for efficiently generating test components for testing and evaluating a design under test. As a design is being configured, generated test components are made available. In one example, test components are automatically generated and included in a simulation testbench based on selected components in the design. Generally, the test components complement the selected components in the design. Moreover, the test components can be automatically seeded with…
PROGRAMMABLE LOGIC DEVICE WITH SERIAL INTERCONNECT
Granted: August 16, 2007
Application Number:
20070188189
In a programmable logic device, some or all of the parallel interconnect resources are replaced by serial interconnect resources within the device. Some or all of the functional blocks on the device are supplemented with serial interfaces. Although this makes the functional blocks more complex, it allows a significant reduction in the area consumed by interconnect resources. This translates into a significant reduction in device power consumption. The serial interfaces may operate…
Specialized processing block for programmable logic device
Granted: August 9, 2007
Application Number:
20070185951
A specialized processing block for a programmable logic device includes circuitry for performing multiplications and sums thereof, as well as circuitry for rounding the result. The rounding circuitry can selectably perform round-to-nearest and round-to-nearest-even operations. In addition, the bit position at which rounding occurs is preferably selectable. The specialized processing block preferably also includes saturation circuitry to prevent overflows and underflows, and the bit…
Specialized processing block for programmable logic device
Granted: August 9, 2007
Application Number:
20070185952
A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured…
Modular I/O bank architecture
Granted: July 19, 2007
Application Number:
20070164784
A programmable device I/O architecture allows for a variable number of I/O banks. Each I/O bank is of an I/O bank type. Each I/O bank type has a fixed number of I/O pins. I/O banks of the same I/O type are compatible within the same programmable device and between different types of programmable devices. The number of I/O pins for each I/O bank type is selected so that each of a set of interfaces can be implemented efficiently using I/O banks of at least one I/O bank type. The largest…
Methods and Apparatus for Video Decoding
Granted: July 5, 2007
Application Number:
20070154104
Techniques for performing the processing of blocks of video in multiple stages. Each stage is executed for blocks of data in the frame that need to go through that stage, based on the coding type, before moving to the next stage. This order of execution allows blocks of data to be processed in a nonsequential order, unless the blocks need to go through the same processing stages. Multiple processing elements (PEs) operating in SIMD mode executing the same task and operating on different…
Digitally Programmable Delay Circuit with Process Point Tracking
Granted: June 28, 2007
Application Number:
20070146041
A digitally programmable delay circuit comprising a plurality of transistors connected in parallel with each other and to a line carrying a signal having an edge to be delayed. One or more of the transistors are selected by a delay control signal to impose a delay amount to the edge, wherein the delay control signal is based on a desired delay amount and a measure of instantaneous process, voltage and temperature conditions of an integrated circuit in which the plurality of transistors…
Signal adjustment receiver circuitry
Granted: June 28, 2007
Application Number:
20070147478
Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the…
Manifold Array Processor
Granted: June 28, 2007
Application Number:
20070150698
An array processor includes processing elements (00, 01, 02, 03, 10, 11, 12, 13, 20, 21, 23, 30, 31, 32, 33) arranged in clusters (e.g., 44, 46, 48, 50) to form a rectangular array (40). Inter-cluster communication paths (88) are mutually exclusive. Due to the mutual exclusivity of the data paths, communications between the processing elements of each cluster may be combined in a single inter-cluster path, thus eliminating half the wiring required for the path. The length of the longest…
Next generation 8B10B architecture
Granted: June 21, 2007
Application Number:
20070139232
Eight-bit ten-bit (8B10B) coding is provided in a hard intellectual property (IP) block with the capability of supporting a greater range of data rates (e.g., data rates less than, equal to, and greater than 3.125 Gbps). Each channel of high speed serial interface circuitry includes receiver circuitry having two 8B10B decoders and transmitter circuitry having two 8B10B encoders. The receiver and transmitter circuitry can be configured to operate in one of three modes of operation:…
Systems and methods for reducing static and total power consumption in a programmable logic device
Granted: May 3, 2007
Application Number:
20070101175
A method and system for reducing power consumption in a programmable logic device (PLD) is provided. The power consumption may be reduced by preferably continually considering power consumption as a factor in circuit design during the technology mapping, routing, and period following routing of the programmable logic device.
BIDIRECTIONAL WAVELENGTH CROSS CONNECT ARCHITECTURES USING WAVELENGTH ROUTING ELEMENTS
Granted: April 19, 2007
Application Number:
20070086781
Bidirectional wavelength cross connects include a plurality of ports, each configured to receive an input optical signals, each input optical signal having a plurality of spectral bands. At least one of the plurality of ports is disposed to simultaneously transmit an output optical signal having at least one of the spectral bands. A plurality of wavelength routing elements are configured to selectively route input optical signal spectral bands to output optical signals.
Methods and Apparatus for Providing Data Transfer Control
Granted: April 19, 2007
Application Number:
20070088868
A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for…
Area efficient fractureable logic elements
Granted: March 22, 2007
Application Number:
20070063732
A fracturable logic element includes a first, second, third, and fourth two-input lookup tables (2-LUTs). Each 2-LUT includes four memory elements. Each memory element is configured to hold one data bit. The fracturable logic element also includes a set of six inputs and a control circuit configured to operate in a first mode and a second mode. When the control circuit operates in the first mode, a first combinatorial output is generated using four of the set of six inputs and the first,…
Fast method for functional mapping to incomplete LUT pairs
Granted: February 15, 2007
Application Number:
20070035327
A configuration for a programmable device is determined to implement an incomplete function using at least two logic cells. Function inputs are partitioned into portions associated with first and second logic cells. The partitioning is screened to determine if it is potentially acceptable by determining if a portion of the function can be implemented using a complete look-up table. If the partitioning of the function inputs is potentially acceptable, the function inputs are assigned to…
Reducing false positives in configuration error detection for programmable devices
Granted: January 11, 2007
Application Number:
20070011578
A device reduces false positive memory error detections by using a masking unit and sensitivity mask data to exclude unused portions of the memory from the error detection computations. A device includes an error detection unit to read data from the memory and verify data integrity. The sensitivity mask data indicates unused portions of the memory. Unused portions of the memory may correspond with configuration data for unused portions of a programmable device. Each bit of the…
Smaller and faster comparators
Granted: December 21, 2006
Application Number:
20060288061
Adder units are used to compare two numbers. A first logic unit receives one or more bits from a first number and the bits from a second number less the least significant bit of that second number. A second logic unit receives one or more bits from the second number and the bits from the first number less the least significant bit of that first number. The logic units generate, based on the logic values (bits) input into the logic units, logic values and output those values to an adder…
Pipelined scan structures for testing embedded cores
Granted: December 14, 2006
Application Number:
20060282729
A scan testing technique in which test data is pipelined to scan logic within an integrated circuit. In system on a programmable chip (SOPC) designs, pipelines are easily built in the programmable logic device (PLD) logic by configuring programmable interconnects to connect registers in a pipelined manner so that test data can be pipelined to scan the logic under test. In system on a chip (SOC) designs, a smart test generator-analyzer is configured to recursively extract pipeline…
Dynamic RAM storage techniques
Granted: November 2, 2006
Application Number:
20060245238
Dynamic RAM (DRAM) cells are provided. Data can be read from a DRAM cell without draining the stored charge stored in the cell. During a read cycle, current flows between a Read Bit line and a supply voltage, and charge is not drained directly from the DRAM storage node. Each DRAM cell has a small number of transistors. The DRAM cell can be used to store configuration data on a programmable integrated circuits (IC). Pass gates are used on programmable ICs to drive signals across the…
Methods and apparatus for design entry and synthesis of digital circuits
Granted: October 26, 2006
Application Number:
20060242616
Methods and apparatus are provided for design entry and synthesis of components, such as components implemented on a programmable chip. In one example, a design tool receives natural or intuitive parameters describing characteristics of a component in a design. Natural or intuitive parameters include input data rate, output latency, footprint, etc. Non-natural or non-intuitive parameters such as clock rate and pipeline stages need not be provided. The design tool automatically selects…
