DYNAMIC CLOCK-DATA PHASE ALIGNMENT IN A SOURCE SYNCHRONOUS INTERFACE CIRCUIT
Granted: February 8, 2018
Application Number:
20180041328
The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. Clock-data phase alignment circuitry is presented that may receive a differential clock with complementary…
Techniques For Generating Pulse-Width Modulation Data
Granted: February 8, 2018
Application Number:
20180041201
An integrated circuit includes a control circuit, a first-in first-out circuit, and a serializer circuit. The control circuit generates parallel pulse-width modulation data in first parallel pulse-width modulation signals. The first-in first-out circuit stores the parallel pulse-width modulation data indicated by the first parallel pulse-width modulation signals. The first-in first-out circuit outputs the stored parallel pulse-width modulation data in second parallel pulse-width…
CIRCUIT DESIGN INSTRUMENTATION FOR STATE VISUALIZATION
Granted: January 4, 2018
Application Number:
20180004878
An integrated circuit includes user storage circuits, a local control circuit, and scan storage circuits arranged in a scan chain. At least a portion of a design-under-test is implemented in a subset of the integrated circuit that comprises the user storage circuits. The local control circuit retrieves data stored in the user storage circuits through the scan storage circuits without erasing the data stored in the user storage circuits after halting oscillations in a user clock signal…
METHOD AND APPARATUS FOR PHASE-ALIGNED 2X FREQUENCY CLOCK GENERATION
Granted: December 28, 2017
Application Number:
20170373675
One embodiment relates to a multiple-channel serializer circuit that includes a plurality of one-channel serializers. A one-channel serializer of the plurality of one-channel serializes includes a local 2× frequency clock generator with a non-divider structure. Other embodiments relate to methods of using a non-divider circuit to generate a local 2× frequency clock signal in a one-channel serializer of a multiple-channel serializer. Another embodiment relates to a local 2× frequency…
METHOD AND APPARATUS FOR DATA DETECTION AND EVENT CAPTURE
Granted: December 28, 2017
Application Number:
20170371818
One embodiment relates to a data detection and event capture circuit. Data comparator logic receives a monitored data word from a parallel data bus and generates a plurality of pattern detected signals. Any pattern detection logic receives the plurality of pattern detected signals and generates a plurality of any pattern detected signals. Sequence detection logic receives the plurality of pattern detected signals and generates a plurality of sequence detected signals. Another embodiment…
METHODS AND APPARATUS FOR SMART MEMORY INTERFACE
Granted: December 28, 2017
Application Number:
20170371594
One embodiment relates to a memory structure that includes a bank group and a port emulation circuit module. The bank group includes a plurality of memory banks, each memory bank having one read port and one write port. The port emulation circuit module provides a group read/write port and a group read port for the bank group. Another embodiment relates to a port emulation circuit module. The port emulation circuit module includes a port emulation control circuit that receives control…
TECHNIQUES FOR DETECTING AND CORRECTING ERRORS ON A RING OSCILLATOR
Granted: December 21, 2017
Application Number:
20170366174
A circuit may include a ring oscillator circuit and monitoring circuitry. The ring oscillator circuit has a group of inverters in a loop, whereby the group of inverters includes first, second, and third output nodes. The monitoring circuitry may monitor for error events in a signal that has passed through the inverters from any one of the first, second, or third output nodes, and may generate first and second monitoring circuitry outputs. The circuit may further include an error…
LOW-SKEW CHANNEL BONDING USING PHASE-MEASURING FIFO BUFFER
Granted: December 7, 2017
Application Number:
20170353335
Circuits and methods are disclosed for low-skew bonding of a plurality of data channels into a multi-lane data channel. In one embodiment, phase-measuring first-in first-out buffer circuits buffer pre-buffer parallel data signals and generate phase-measurement signals. A channel-bonding control circuit receives the phase-measurement signals and generates bit-slip control signals. Transmission bit-slip circuits slip integer numbers of bits based on the bit-slip control signals. Bypass…
Current Limited Power Converter Circuits And Methods
Granted: November 16, 2017
Application Number:
20170331363
A power converter circuit regulates an output voltage of a power train circuit and controls the current in the power train circuit. A current sensor circuit measures a current in the power train circuit. A hysteretic comparison circuit compares the current in the power train circuit to positive and negative current limits. The hysteretic comparison circuit causes a positive current in the power train circuit to decrease in a positive current limit mode in response to the positive current…
PIPELINED CASCADED DIGITAL SIGNAL PROCESSING STRUCTURES AND METHODS
Granted: November 9, 2017
Application Number:
20170322813
Circuitry operating under a floating-point mode or a fixed-point mode includes a first circuit accepting a first data input and generating a first data output. The first circuit includes a first arithmetic element accepting the first data input, a plurality of pipeline registers disposed in connection with the first arithmetic element, and a cascade register that outputs the first data output. The circuitry further includes a second circuit accepting a second data input and generating a…
FIXED-POINT AND FLOATING-POINT ARITHMETIC OPERATOR CIRCUITS IN SPECIALIZED PROCESSING BLOCKS
Granted: November 9, 2017
Application Number:
20170322769
The present embodiments relate to circuitry that efficiently performs floating-point arithmetic operations and fixed-point arithmetic operations. Such circuitry may be implemented in specialized processing blocks. If desired, the specialized processing blocks may include configurable interconnect circuitry to support a variety of different use modes. For example, the specialized processing block may efficiently perform a fixed-point or floating-point addition operation or a portion…
CIRCUITRY AND METHODS FOR IMPLEMENTING GALOIS-FIELD REDUCTION
Granted: November 2, 2017
Application Number:
20170315781
Galois-field reduction circuitry for reducing a Galois-field expansion value, using an irreducible polynomial, includes a plurality of memories, each for storing a respective value derived from the irreducible polynomial and a respective combination of expansion bit values, wherein expansion bits of the expansion value address the plurality of memories to output one or more of the respective values. The Galois-field reduction circuitry also includes exclusive-OR circuitry for combining…
PIPELINED CASCADED DIGITAL SIGNAL PROCESSING STRUCTURES AND METHODS
Granted: October 19, 2017
Application Number:
20170300337
Circuitry operating under a floating-point mode or a fixed-point mode includes a first circuit accepting a first data input and generating a first data output. The first circuit includes a first arithmetic element accepting the first data input, a plurality of pipeline registers disposed in connection with the first arithmetic element, and a cascade register that outputs the first data output. The circuitry further includes a second circuit accepting a second data input and generating a…
ADAPTIVE REFRESH SCHEDULING FOR MEMORY
Granted: October 5, 2017
Application Number:
20170287543
The present disclosure provides for adaptive scheduling of memory refreshes. One embodiment relates to a method of adapting an initial refresh sequence. In this method, flow and blockage scores for each refresh sequence of a plurality of refresh sequences are obtained and stored in an array of scores. An initial refresh sequence is selected in a way that favors a high flow score and a low blockage score. Another embodiment relates to a method of adapting a current refresh sequence.…
Techniques For Enabling And Disabling Transistor Legs In An Output Driver Circuit
Granted: September 14, 2017
Application Number:
20170264283
An output driver circuit includes a control circuit and first and second transistor legs that are coupled to an output pad. Each of the first and second transistor legs includes a pull-up transistor and a pull-down transistor. The control circuit is coupled to the first and second transistor legs. The control circuit enables the first transistor leg to generate an output signal at the output pad and disables the second transistor leg during a first phase of a cycle. The control circuit…
STATE VISIBILITY AND MANIPULATION IN INTEGRATED CIRCUITS
Granted: September 14, 2017
Application Number:
20170262563
In a first mode, a control circuit may implement a circuit design with storage circuits in an integrated circuit by programming configuration memory bits via configuration resources. The storage circuits may be accessed for read and write operations during the execution of the circuit design implementation with the integrated circuit. In a second mode, the control circuit may perform read and write access operations at the storage circuits via configuration resources or via an interface…
Techniques For Protecting Security Features of Integrated Circuits
Granted: September 7, 2017
Application Number:
20170257222
An integrated circuit includes a control circuit, a one-time programmable circuit, and a security feature. The control circuit determines if the one-time programmable circuit is programmed in response to a request by a user of the integrated circuit to access the security feature. The control circuit generates a signal to indicate to the user of the integrated circuit that the security feature has been previously accessed if the control circuit determines that the one-time programmable…
MULTI-ACCESS MEMORY SYSTEM AND A METHOD TO MANUFACTURE THE SYSTEM
Granted: August 31, 2017
Application Number:
20170250155
A multiple memory access system is disclosed. The system includes a first die disposed on a package substrate. A second die is stacked above the first die. The first die, the second die and the package substrate form a first package. An IC is placed within a close proximity of the first package where the first die communicates with the second die at a first data rate while the first die communicates with the IC at a second data rate. The first data rate is higher than the second data…
METHODS AND APPARATUS FOR PERFORMING REED-SOLOMON ENCODING
Granted: August 31, 2017
Application Number:
20170250713
The present embodiments relate to Reed-Solomon encoding, and to circuitry for performing such encoding, particularly in an integrated circuit. A Reed-Solomon encoder circuit may receive a message with data symbols and compute a partial syndrome vector by multiplying the data symbols with a first matrix. The Reed-Solomon encoder circuit may further compute parity check symbols by solving a system of linear equations that includes the partial syndrome vector and a second matrix. As an…
TECHNIQUES FOR DETECTING AND CORRECTING ERRORS ON A RING OSCILLATOR
Granted: August 31, 2017
Application Number:
20170250681
A circuit may include a ring oscillator circuit and monitoring circuitry. The ring oscillator circuit has a group of inverters in a loop, whereby the group of inverters includes first, second, and third output nodes. The monitoring circuitry may monitor for error events in a signal that has passed through the inverters from any one of the first, second, or third output nodes, and may generate first and second monitoring circuitry outputs. The circuit may further include an error…
