DENORMALIZATION IN MULTI-PRECISION FLOATING-POINT ARITHMETIC CIRCUITRY
Granted: August 15, 2019
Application Number:
20190250886
The present embodiments relate to integrated circuits with floating-point arithmetic circuitry that handles normalized and denormalized floating-point numbers. The floating-point arithmetic circuitry may include a normalization circuit and a rounding circuit, and the floating-point arithmetic circuitry may generate a first result in form of a normalized, unrounded floating-point number and a second result in form of a normalized, rounded floating-point number. If desired, the…
METHOD FOR DISTRIBUTING A LOAD IN A MULTI RADIO ACCESS TECHNOLOGY HETEROGENEOUS NETWORK
Granted: March 7, 2019
Application Number:
20190075570
A method for distributing the traffic load in a multi radio access technology heterogeneous network, the network including macrocells operating in a first sub-6 GHz band, and minicells that can operate in the sub-6 GHz band and in a millimeter band. The distribution of the traffic is carried out with an association strategy that calls upon, on the first hand, a first bias (QT) in order to favour the association with the base stations of the minicells/macrocells and a second bias (QR) in…
Techniques For Protecting Security Features of Integrated Circuits
Granted: January 24, 2019
Application Number:
20190026497
An integrated circuit includes a control circuit and a one-time programmable circuit. The control circuit determines if the one-time programmable circuit is programmed in response to an attempt to access a mode of the integrated circuit after the integrated circuit powers up. The control circuit generates a signal to indicate to a user of the integrated circuit that the mode of the integrated circuit has been previously accessed if the control circuit determines that the one-time…
PROGRAMMABLE INTEGRATED CIRCUITS WITH IN-OPERATION RECONFIGURATION CAPABILITY
Granted: January 17, 2019
Application Number:
20190018063
Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In…
METHODS AND APPARATUS FOR PERFORMING PRODUCT SERIES OPERATIONS IN MULTIPLIER ACCUMULATOR BLOCKS
Granted: November 29, 2018
Application Number:
20180341461
A specialized processing block on an integrated circuit includes a first and second arithmetic operator stage, an output coupled to another specialized processing block, and configurable interconnect circuitry which may be configured to route signals throughout the specialized processing block, including in and out of the first and second arithmetic operator stages. The configurable interconnect circuitry may further include multiplexer circuitry to route selected signals. The output of…
Apparatus For Flexible Electronic Interfaces And Associated Methods
Granted: November 22, 2018
Application Number:
20180337681
A semiconductor die includes at least one flexible interface block. The flexible interface block includes at least one interconnect, and at least one buffer coupled to the at least one interconnect. The flexible interface block further includes a routing interface coupled to circuitry integrated in the semiconductor die, and a controller coupled to provide communication between the routing interface and the at least one buffer.
SCALABLE 2.5D INTERFACE CIRCUITRY
Granted: August 23, 2018
Application Number:
20180239738
A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to…
COAXIAL AND DOUBLE LUMEN BREATHING CIRCUIT SYSTEMS HAVING A LUNG PRESSURE MEASUREMENT PORT AND CLOSED SYSTEM WATER TRAP WHICH CAN BE DRAINED WITH AN ENJECTOR
Granted: August 9, 2018
Application Number:
20180221615
The invention relates to providing novel functions to the double lumen breathing circuits and coaxial breathing circuits which at present do not comprise water traps, by adding a closed system water trap designed to have an inkwell shape and a lung pressure measurement port to said circuits wherein the fluid collected in the bottle section can be discharged without having to open the bottle by means of a drainage luer port located at the base of the bottle and a needleless apparatus that…
DENORMALIZATION IN MULTI-PRECISION FLOATING-POINT ARITHMETIC CIRCUITRY
Granted: May 3, 2018
Application Number:
20180121168
The present embodiments relate to integrated circuits with floating-point arithmetic circuitry that handles normalized and denormalized floating-point numbers. The floating-point arithmetic circuitry may include a normalization circuit and a rounding circuit, and the floating-point arithmetic circuitry may generate a first result in form of a normalized, unrounded floating-point number and a second result in form of a normalized, rounded floating-point number. If desired, the…
Techniques For Handling High Voltage Circuitry In An Integrated Circuit
Granted: April 19, 2018
Application Number:
20180109262
An integrated circuit formed using a semiconductor substrate may include a logic circuit and a switch circuit, whereby the logic circuit operates at a first power supply voltage and the switch circuit operates at a second power supply voltage that is greater than the first power supply voltage. The logic circuit may be formed within a first triple well structure within the semiconductor substrate and is supplied with a first bias voltage. The switch circuit may be formed within a second…
Fluid Routing Devices And Methods For Cooling Integrated Circuit Packages
Granted: March 29, 2018
Application Number:
20180090417
A fluid routing device includes a fluid inlet, first vertical channels, a horizontal channel, a second vertical channel, and a fluid outlet. The first vertical channels are open to the fluid inlet. The horizontal channel is open to each of the first vertical channels. The first vertical channels are oriented to provide fluid coolant from the fluid inlet vertically down to the horizontal channel. The horizontal channel is open on one side such that fluid coolant in the horizontal channel…
SMART DIAGNOSIS OF INTEGRATED CIRCUITS INCLUDING IP CORES WITH ENCRYPTED SIMULATION MODELS
Granted: March 29, 2018
Application Number:
20180089352
The present embodiments relate to methods for simulating the behavior of an IP core that has an encrypted simulation model. The encrypted simulation model of the IP core may include a plurality of probes, which a debug option may activate selectively, if desired. The encrypted simulation model may collect data during a simulation as selected by the activated probes of the plurality of probes. The encrypted simulation model may perform smart diagnosis of the collected data based on a set…
Techniques For Power Control Of Circuit Blocks
Granted: March 22, 2018
Application Number:
20180083626
An integrated circuit includes a circuit block, a storage circuit that stores a static power gating control signal, a logic gate circuit that receives a dynamic power gating control signal and the static power gating control signal from the storage circuit, and a transistor coupled between the circuit block and a supply node at a supply voltage. A conductive state of the transistor is determined by an output signal of the logic gate circuit. The transistor is turned off to provide power…
REDUCED FLOATING-POINT PRECISION ARITHMETIC CIRCUITRY
Granted: March 22, 2018
Application Number:
20180081632
The present embodiments relate to performing reduced-precision floating-point arithmetic operations using specialized processing blocks with higher-precision floating-point arithmetic circuitry. A specialized processing block may receive four floating-point numbers that represent two single-precision floating-point numbers, each separated into an LSB portion and an MSB portion, or four half-precision floating-point numbers. A first partial product generator may generate a first partial…
DISTRIBUTED DOUBLE-PRECISION FLOATING-POINT MULTIPLICATION
Granted: March 22, 2018
Application Number:
20180081631
The present embodiments relate to circuitry that efficiently performs double-precision floating-point multiplication operations, single-precision floating-point multiplication operations, and fixed-point multiplication operations. Such circuitry may be implemented in specialized processing blocks. If desired, each specialized processing block efficiently may perform a single-precision floating-point multiplication operation, and multiple specialized processing blocks may be coupled…
DYNAMIC CLOCK-DATA PHASE ALIGNMENT IN A SOURCE SYNCHRONOUS INTERFACE CIRCUIT
Granted: February 8, 2018
Application Number:
20180041328
The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. Clock-data phase alignment circuitry is presented that may receive a differential clock with complementary…
Techniques For Generating Pulse-Width Modulation Data
Granted: February 8, 2018
Application Number:
20180041201
An integrated circuit includes a control circuit, a first-in first-out circuit, and a serializer circuit. The control circuit generates parallel pulse-width modulation data in first parallel pulse-width modulation signals. The first-in first-out circuit stores the parallel pulse-width modulation data indicated by the first parallel pulse-width modulation signals. The first-in first-out circuit outputs the stored parallel pulse-width modulation data in second parallel pulse-width…
CIRCUIT DESIGN INSTRUMENTATION FOR STATE VISUALIZATION
Granted: January 4, 2018
Application Number:
20180004878
An integrated circuit includes user storage circuits, a local control circuit, and scan storage circuits arranged in a scan chain. At least a portion of a design-under-test is implemented in a subset of the integrated circuit that comprises the user storage circuits. The local control circuit retrieves data stored in the user storage circuits through the scan storage circuits without erasing the data stored in the user storage circuits after halting oscillations in a user clock signal…
METHOD AND APPARATUS FOR DATA DETECTION AND EVENT CAPTURE
Granted: December 28, 2017
Application Number:
20170371818
One embodiment relates to a data detection and event capture circuit. Data comparator logic receives a monitored data word from a parallel data bus and generates a plurality of pattern detected signals. Any pattern detection logic receives the plurality of pattern detected signals and generates a plurality of any pattern detected signals. Sequence detection logic receives the plurality of pattern detected signals and generates a plurality of sequence detected signals. Another embodiment…
METHOD AND APPARATUS FOR PHASE-ALIGNED 2X FREQUENCY CLOCK GENERATION
Granted: December 28, 2017
Application Number:
20170373675
One embodiment relates to a multiple-channel serializer circuit that includes a plurality of one-channel serializers. A one-channel serializer of the plurality of one-channel serializes includes a local 2× frequency clock generator with a non-divider structure. Other embodiments relate to methods of using a non-divider circuit to generate a local 2× frequency clock signal in a one-channel serializer of a multiple-channel serializer. Another embodiment relates to a local 2× frequency…
