METHOD AND APPARATUS FOR SECURING CONFIGURATION SCAN CHAINS OF A PROGRAMMABLE DEVICE
Granted: January 29, 2015
Application Number:
20150033360
Scan chain circuitry on an integrated circuit device includes a plurality of memory elements, and a plurality of control elements. Each of the control elements is located between respective ones of the plurality of memory elements for controllably connecting the plurality of memory elements into a scan chain. A plurality of respective scan enable activation elements controls a respective subplurality of the plurality of control elements for connecting a respective subplurality of the…
Method and Apparatus for Implementing a System-Level Design Tool for Design Planning and Architecture Exploration
Granted: December 25, 2014
Application Number:
20140379307
A method for designing a system on a target device includes mapping a high-level description of the system onto a model of a target device prior to generating a register transfer level description of the system. A visual representation of the mapping is generated.
Integrated Circuits With On-Die Decoupling Capacitors
Granted: December 25, 2014
Application Number:
20140374877
An integrated circuit includes a decoupling capacitor and an internal circuit. The decoupling capacitor is coupled to a first external terminal of the integrated circuit. The internal circuit in the integrated circuit is coupled to a second external terminal of the integrated circuit. The decoupling capacitor is coupled to provide supply voltage current to the internal circuit through the first and the second external terminals and through external conductors. The external conductors are…
BRIDGE CIRCUITRY FOR COMMUNICATIONS WITH DYNAMICALLY RECONFIGURABLE CIRCUITS
Granted: December 18, 2014
Application Number:
20140372654
A bridge circuit may be used to interface between dynamically reconfigurable circuitry and dedicated circuitry or other circuitry having static configurations during normal operation of the device. The bridge circuit may include interface circuitry coupled between first and second interfaces that communicate with the dynamically reconfigurable circuitry and the dedicated circuitry. Control circuitry may control the interface circuitry based on variable communications requirements of the…
Systems and Methods for Intermediate Message Authentication in a Switched-Path Network
Granted: December 4, 2014
Application Number:
20140359297
Systems, methods, and devices are provided for intermediate authentication of a message transmitted through a switched-path network, such as an optical transport network (OTN). In one method, a message transmitted through communication nodes of a switched-path network may be authenticated, at least partially, by authentication logic of one or more of the communication nodes. The one or more communication nodes may identify whether a prior communication node has tampered with or corrupted…
Cache Memory Controller for Accelerated Data Transfer
Granted: December 4, 2014
Application Number:
20140359219
A cache memory controller in a computer system, such as a multicore processing system, provides compression for writes to memory, such as an off-chip memory, and decompression after reads from memory. Application accelerator processors in the system generate application data and requests to read/write the data from/to memory. The cache memory controller uses information relating location parameters of buffers allocated for application data and sets parameters to configure compression and…
Data Encoding for Attenuating Image Encoders
Granted: December 4, 2014
Application Number:
20140355683
A hybrid access encoder includes one or more improvements to attenuation-based image and video encoders using images. The hybrid access encoder supports tradeoffs between encoded bit rate and decoded image and video quality. The hybrid access encoder monitors multiple redundancy removal filters and selects the best-performing filter for encoding. The hybrid access encoder operates in a mode that specifies a target decoded image quality and a target encoded bit rate, giving preference to…
Adaptive Video Reference Frame Compression with Control Elements
Granted: December 4, 2014
Application Number:
20140355665
An access encoder reduces power consumption during video playback and recording by reducing the bandwidth between a processor and a memory. A graphical user interface allows user selection, or software control, over the tradeoff between battery life and video quality. Battery life can be increased (decreased) by activating the access encoder. The access encoder may be implemented in a microprocessor, graphics processor, digital signal processor, FPGA, ASIC, or SoC. The access encoder's…
EFFICIENT 2D ADAPTIVE NOISE THRESHOLDING FOR VIDEO PROCESSING
Granted: October 9, 2014
Application Number:
20140300818
Various embodiments of the present disclosure provide techniques for performing video denoising (VDN). An adaptive noise threshold is dynamically determined and used to distinguish between frame to frame differences in pixel values that relate to image motion from those differences that relate to noise. The disclosed techniques enable the noise threshold to be continuously updated, for example as frequently as once per frame, so that the noise threshold may closely track to varying…
Hybrid Programmable Many-Core Device with On-Chip Interconnect
Granted: September 18, 2014
Application Number:
20140281379
The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The…
APPARATUS FOR IMPROVED COMMUNICATION AND ASSOCIATED METHODS
Granted: September 18, 2014
Application Number:
20140269983
An apparatus includes a transmitter adapted to transmit encoded information to a communication link. The transmitter includes a DC balance skew generator. The DC balance skew generator is adapted to skew a DC balance of the information before information is provided to the communication link.
DIGITAL EQUALIZER ADAPTATION USING ON-DIE INSTRUMENT
Granted: September 18, 2014
Application Number:
20140269890
Systems and methods are provided for adjusting gain of a receiver. Adaptation circuitry is operable to identify, based on a matrix representation of a receiver's output generated from horizontal and vertical sweeps of the receiver's output, an eye opening of the receiver's output. The adaptation circuitry is also operable to determine whether a size of the eye opening needs to be changed. When it is determined that the size of the eye opening needs to be changed, the adaptation circuitry…
METHODS TO ACHIEVE ACCURATE TIME STAMP IN IEEE 1588 FOR SYSTEM WITH FEC ENCODER
Granted: September 18, 2014
Application Number:
20140269778
Systems and methods and systems are disclosed for allowing the medium access control (MAC) layer in a communication system within an integrated circuit or device to accurately determine a timestamp point and a timestamp value when, for example, the Precision Time Protocol (PTP) protocol is in use by the communication system. Such determination of accurate timestamp point and timestamp value may be used by the communication system to account for and to compensate for the time shift(s)…
APPARATUS FOR ELECTRONIC ASSEMBLY WITH IMPROVED INTERCONNECT AND ASSOCIATED METHODS
Granted: September 18, 2014
Application Number:
20140264783
An apparatus includes a substrate that includes electronic circuitry. The apparatus further includes a first die that includes electronic circuitry, and at least one shielded interconnect. The shielded interconnect(s) couple(s) electronic circuitry in the substrate to electronic circuitry in the first die.
APPARATUS AND METHODS FOR POWER MANAGEMENT IN INTEGRATED CIRCUITS
Granted: September 11, 2014
Application Number:
20140258956
A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.
SUB-RATE MAPPING FOR LOWEST-ORDER OPTICAL DATA UNIT
Granted: September 11, 2014
Application Number:
20140255028
One embodiment relates a method for communicating data using an optical transport network. Multiple sub-rate client data signals are received from client sources. The sub-rate client data signals each have a data rate which is less than a data rate capacity of a lowest-order data unit. A predetermined number of tributary slots are provided in the lowest-order optical channel data unit, and each sub-rate client data signal are mapped to at least one of the tributary slots. Another…
HEAT SPREADING IN MOLDED SEMICONDUCTOR PACKAGES
Granted: August 28, 2014
Application Number:
20140239483
A molded semiconductor package comprises a substrate, a semiconductor die mounted on the substrate, a molding compound encircling the die on the substrate, and one or more heat conductors in the molding compound that are thermally coupled to the substrate. Advantageously, the heat conductors are mounted in the molding compound near one or more of the corners of the die. The package may also include a lid. The heat conductors produce a more uniform distribution of heat in the substrate.…
CONFIGURING A PROGRAMMABLE LOGIC DEVICE USING A CONFIGURATION BIT STREAM WITHOUT PHANTOM BITS
Granted: August 28, 2014
Application Number:
20140245246
Techniques and mechanisms generate a configuration bit stream to load into a circuit such as a Programmable Logic Device (PLD). A configuration bit stream may have a reduced size if “phantom bits” not corresponding to configuration elements are removed. However, the PLD may need a full-sized and properly ordered configuration bit stream in order to be properly configured. Techniques and mechanisms are described for selectively adding a “padding bit” to compensate for the missing…
Memory Array with Redundant Bits and Memory Element Voting Circuits
Granted: August 28, 2014
Application Number:
20140245113
An integrated circuit may have an array of memory elements. Each memory element may have multiple memory cells. Each memory element may have a voting circuit that receives signals from the memory cells in that memory element. The voting circuit can produce an output based on the signals. The signals stored by the memory cells of each memory element may be redundant so that the voting circuit can produce an accurate output even in the event that a radiation strike causes some of the…
HEAT PIPE IN OVERMOLDED FLIP CHIP PACKAGE
Granted: August 28, 2014
Application Number:
20140239487
The present invention is an improvement in a molded semiconductor package and the method for its manufacture. The package comprises a substrate, a semiconductor die mounted on the substrate, a molding compound encircling the die on the substrate, a lid on the molding compound, and a heat pipe extending between the semiconductor die and the lid. Preferably, the heat pipe is formed so that it encircles the die. The package is assembled by mounting the die on the substrate, applying the…
