Method and Apparatus for Performing Parallel Routing Using a Multi-Threaded Routing Procedure
Granted: August 7, 2014
Application Number:
20140223403
A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.
APPARATUS AND METHODS FOR COMMUNICATING WITH PROGRAMMABLE DEVICES
Granted: August 7, 2014
Application Number:
20140223034
A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.
Techniques For Alignment of Parallel Signals
Granted: August 7, 2014
Application Number:
20140218221
Receiver circuits in serial lanes each generate a synchronous clock signal that is aligned with a master clock signal to allow synchronous transfer of data onto the master clock domain without corruption. A serial-to-parallel converter circuit in each receiver circuit converts a serial data signal into parallel data signals in response to one of the synchronous clock signals. Phase detection circuitry generates an indication of a phase shift based on a phase offset between the…
ADAPTABLE DATAPATH FOR A DIGITAL PROCESSING SYSTEM
Granted: July 31, 2014
Application Number:
20140215180
The present invention includes an adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with…
PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS
Granted: July 31, 2014
Application Number:
20140210515
In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
BYPASSABLE CLOCKED STORAGE CIRCUITRY FOR DYNAMIC VOLTAGE-FREQUENCY SCALING
Granted: July 31, 2014
Application Number:
20140210510
Integrated circuits with sequential logic circuitry are provided. Sequential logic circuitry may include a chain of bypassable clocked storage elements coupled between a speed critical input terminal and a speed critical output terminal. Combinational logic circuits may be interposed between each adjacent pair of bypassable clocked storage elements in the chain. Dynamic voltage-frequency scaling (DVFS) control circuitry may provide an adjustable power supply voltage to the combinational…
INTEGRATED CIRCUIT PACKAGE WITH ACTIVE INTERPOSER
Granted: July 31, 2014
Application Number:
20140210097
An integrated circuit package may include a substrate and an interposer. The interposer is disposed over the substrate. The interposer may include embedded switching elements that may be used to receive different power supply signals. An integrated circuit with multiple logic blocks is disposed over the substrate. The switching elements embedded in the interposer may be used to select a power supply signal from the power supply signals and may be used to provide at least one circuit…
METAL-PROGRAMMABLE INTEGRATED CIRCUITS
Granted: July 17, 2014
Application Number:
20140197463
A metal-programmable integrated circuit may include an array of metal-programmable cells. Each cell may include multi-gate transistor structures in which multiple surfaces of a gate structure serve to control current flow through at least one channel structure. The multi-gate transistor structures may form one or more fin-shaped field effect transistors. The gate structure may at least partially enclose multiple channel structures. Pairs of source-drain structures may be coupled to the…
SYSTEMS AND METHODS FOR DETECTING AND MITIGATING PROGRAMMABLE LOGIC DEVICE TAMPERING
Granted: July 17, 2014
Application Number:
20140201852
Systems and methods are disclosed for preventing tampering of a programmable integrated circuit device. Generally, programmable devices, such as FPGAs, have two stages of operation; a configuration stage and a user mode stage. To prevent tampering and/or reverse engineering of a programmable device, various anti-tampering techniques may be employed during either stage of operation to disable the device and/or erase sensitive information stored on the device once tampering is suspected.…
METHODS AND APPARATUS FOR ALIGNING CLOCK SIGNALS ON AN INTEGRATED CIRCUIT
Granted: July 17, 2014
Application Number:
20140198810
A method of aligning clock signals in multiple transceiver channels on an integrated circuit may include adjusting a slave clock signal at a slave transceiver channel based on a master clock signal received from a master transceiver channel. A clock generation circuit and/or a delay circuit in the slave transceiver channel may be used to adjust the slave clock signal to produce an intermediate slave clock signal. The master clock signal may be adjusted based on the intermediate slave…
PARTITIONING DESIGNS TO FACILITATE CERTIFICATION
Granted: July 3, 2014
Application Number:
20140189622
This disclosure relates generally to field-programmable gate arrays (FPGAs). Some implementations relate to methods and systems for partitioning FPGA circuit designs to facilitate certification. In one aspect, a method includes generating a hardware description language (HDL) implementation of a circuit design. The method additionally includes partitioning the design into a first portion and a second portion. In some implementations, the second portion corresponds to a safety-critical…
METHOD AND SYSTEM FOR OPERATING A COMMUNICATION CIRCUIT CONFIGURABLE TO SUPPORT ONE OR MORE DATA RATES
Granted: July 3, 2014
Application Number:
20140189459
A method and system for operating a communication circuit that is configurable to support one or more communication standards on a single device. The communication circuit includes a transmitting device that comprises a PCS module operating at a first data rate, and a second PCS module operating at a second data rate. The circuit also includes a plurality of forward error correction (FEC) encoding and decoding modules, each operating at a specified data rate. A first group of FEC…
3D BUILT-IN SELF-TEST SCHEME FOR 3D ASSEMBLY DEFECT DETECTION
Granted: July 3, 2014
Application Number:
20140189456
Techniques and mechanisms are provided for an improved built in self-test (BIST) mechanism for 3D assembly defect detection. According to an embodiment of the present disclosure, the described mechanisms and techniques can function to detect defects in interconnects which vertically connect different layers of a 3D device, as well as to detect defects on a 2D layer of a 3D integrated circuit. Additionally, according to an embodiment of the present disclosure, techniques and mechanisms…
FORWARD ERROR CORRECTION WITH CONFIGURABLE LATENCY
Granted: July 3, 2014
Application Number:
20140189446
A method of performing forward error correction with configurable latency, where a configurable latency algorithm evaluates a target Bit Error Rate (BER) against an actual BER and adjusts the size of a configurable buffer such that the target BER may be achieved when utilizing the smallest buffer size possible. When errors are corrected without the utilization of each of the configurable buffer locations, the algorithm reduces the size of the buffer by y buffer locations; the algorithm…
System and Method for Scheduling and Arbitrating Events in Computing and Networking
Granted: June 26, 2014
Application Number:
20140181126
A method for high-speed scheduling and arbitration of events for computing and networking is disclosed. The method includes the software and hardware implementation of a unique data structure, known as a pile, for scheduling and arbitration of events. According to the method, events are stored in loosely sorted order in piles, with the next event to be processed residing in the root node of the pile. The pipelining of the insertion and removal of events from the piles allows for…
HETEROGENEOUS HIGH-SPEED SERIAL INTERFACE SYSTEM ARCHITECTURE
Granted: June 26, 2014
Application Number:
20140176188
One embodiment relates to an integrated circuit having a plurality of four-channel serial interface modules. Each of the plurality of four-channel serial interface modules includes a first physical medium attachment (PMA) channel circuit, a second PMA channel circuit adjacent to the first PMA channel circuit, a third PMA channel circuit adjacent to the second PMA channel circuit, a fourth PMA channel circuit adjacent to the third PMA channel circuit, and at least one phase-locked loop…
INTEGRATED CIRCUIT DEVICE WITH STITCHED INTERPOSER
Granted: June 26, 2014
Application Number:
20140175666
Systems, methods, and devices are provided to enable an integrated circuit device of relatively higher capacity. Such an integrated circuit device may include at least two component integrated circuits that communicate with one another. Specifically, the component integrated circuits may communicate through a “stitched silicon interposer” that is larger than a reticle limit of the lithography system used to manufacture the interposer. To achieve this larger size, the stitched silicon…
MEMORY ELEMENTS WITH STACKED PULL-UP DEVICES
Granted: June 19, 2014
Application Number:
20140169074
Integrated circuits with memory cells are provided. A memory cell may include first and second cross-coupled inverting circuits configured to store a single data bit. The first inverting circuit may have an output serving as a first data storage node for the memory cell, whereas the second inverting circuit may have an output serving as a second data storage node for the memory cell. Access transistors may be coupled between the first and second data storage nodes and corresponding data…
Methods and Apparatus for Storing Expanded Width Instructions in a VLIW Memory for Deferred Execution
Granted: June 19, 2014
Application Number:
20140173253
Techniques are described for decoupling fetching of an instruction stored in a main program memory from earliest execution of the instruction. An indirect execution method and program instructions to support such execution are addressed. In addition, an improved indirect deferred execution processor (DXP) VLIW architecture is described which supports a scalable array of memory centric processor elements that do not require local load and store units.
APPARATUS AND METHODS FOR EQUALIZER ADAPTATION
Granted: June 19, 2014
Application Number:
20140169439
One embodiment relates to an equalizer circuit for a data link. The equalizer circuit including a continuous-time linear equalizer, a first circuit loop, and a second circuit loop. The continuous-time linear equalizer receives a received signal and outputs an equalized signal. The first circuit loop determines a first average signal amplitude. The first average signal amplitude may be an average signal amplitude of the equalized signal. The second circuit loop a second average signal…
