Fast filtering
Granted: September 25, 2018
Patent Number:
10083007
Devices and methods for filtering data include calculating intermediate input values from input elements using a transformation function. The transformation function is based at least in part on a size of the filter and a number of filter outputs. Intermediate filter values are calculated from filter elements of the filter using the transformation function. Each intermediate input value is multiplied with a respective intermediate filter value to form intermediate values. These…
Mixed redundancy scheme for inter-die interconnects in a multichip package
Granted: September 25, 2018
Patent Number:
10082541
Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a master die that is coupled to one or more slave dies via inter-die package interconnects. A mixed (i.e., active and passive) interconnect redundancy scheme may be implemented to help repair potentially faulty interconnects to improve assembly yield. Interconnects that carry normal user signals may be repaired using an active redundancy scheme by selectively switching into use…
Techniques for variable forward error correction
Granted: September 11, 2018
Patent Number:
10075189
A system includes an encoding circuit, a line quality monitor circuit, and a controller circuit. The encoding circuit generates a first data signal indicating encoded data using a first forward error correction code. The line quality monitor circuit generates an indication of a line quality of a second data signal using an eye monitor circuit that monitors the second data signal. The controller circuit causes the encoding circuit to generate encoded data in the first data signal using a…
Programmable logic device virtualization
Granted: September 11, 2018
Patent Number:
10075167
A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the…
Systems and methods for preventing data remanence in memory systems
Granted: September 11, 2018
Patent Number:
10073989
Methods, circuits, and systems for preventing data remanence in memory systems are provided. Original data is stored in a first memory, which may be a static random access memory (SRAM). Data is additionally stored in a second memory. Data in the first memory is periodically inverted, preventing data remanence in the first memory. The data in the second memory is periodically inverted concurrently with the data in the first memory. The data in the second memory is used to keep track of…
Method and apparatus for performing efficient incremental compilation
Granted: September 11, 2018
Patent Number:
10073941
A method for designing a system on a target device includes identifying candidate portions in the system to preserve based on similarities between the system and another system. Preservation criteria are applied on the candidate portions in the system to preserve to identify portions of the system to preserve. Design results from the another system are reused for portions in the system that are preserved.
Move based XOR optimization
Granted: September 11, 2018
Patent Number:
10073940
A computer-implemented method includes receiving a first circuit design comprising a system of XOR gates, iteratively generating a plurality of candidate physical implementations of the system in adaptive logic modules included in logic array blocks of an integrated circuit, determining an overall metric for each of the plurality of candidate physical implementations using an objective function. The overall metric indicates at least an amount of the system that is implemented by each of…
Reduced floating-point precision arithmetic circuitry
Granted: September 11, 2018
Patent Number:
10073676
The present embodiments relate to performing reduced-precision floating-point arithmetic operations using specialized processing blocks with higher-precision floating-point arithmetic circuitry. A specialized processing block may receive four floating-point numbers that represent two single-precision floating-point numbers, each separated into an LSB portion and an MSB portion, or four half-precision floating-point numbers. A first partial product generator may generate a first partial…
Methods and apparatus for regulating the supply voltage of an integrated circuit
Granted: September 4, 2018
Patent Number:
10068042
The present embodiments relate to regulating the supply voltage of an integrated circuit. The integrated circuit may implement a circuit design. The circuit design implementation may meet timing constraints with timing margins when operated with the integrated circuit at a nominal supply voltage level. The integrated circuit may further include a voltage identification controller. The voltage identification controller may determine a reduced voltage level based at least on the timing…
Systems and methods for designing an integrated circuit
Granted: September 4, 2018
Patent Number:
10068047
A method of designing an integrated circuit using a computer implemented circuit design application is disclosed. The method may involve receiving a user-provided value specifying a number of output components to be connected to an input component in the integrated circuit, connecting the input component to each output component of the number of output components in the integrated circuit using computer-implemented fan-out circuit blocks. In addition, generating a circuit design such…
Non-intrusive monitoring and control of integrated circuits
Granted: September 4, 2018
Patent Number:
10067845
A method of monitoring operations of a set of ICs. The method loads a first set of configuration data into a first IC for configuring a group of configurable circuits of the first IC to perform operations of a user design. The method receives a definition of an event based on values of a set of signals in the user design and a set of corresponding actions to take when the event occurs. The set of signals includes at least one signal received from a second IC. The method generates an…
Method and apparatus for secure provisioning of an integrated circuit device
Granted: August 28, 2018
Patent Number:
10063526
A method of operating an integrated circuit may include generating a session key with a random number generator circuit. The session key may then be used to establish a secure communications channel between the integrated circuit and a remote server. The integrated circuit may be placed in a non-operational mode prior to establishing the secure communications channel. Accordingly, in response to establishing the secure communications channel, the integrated circuit may be placed in an…
Apparatus for flexible electronic interfaces and associated methods
Granted: August 28, 2018
Patent Number:
10063235
A semiconductor die includes at least one flexible interface block. The flexible interface block includes at least one interconnect, and at least one buffer coupled to the at least one interconnect. The flexible interface block further includes a routing interface coupled to circuitry integrated in the semiconductor die, and a controller coupled to provide communication between the routing interface and the at least one buffer.
Systems and methods for multiport to multiport cryptography
Granted: August 28, 2018
Patent Number:
10061941
Systems and methods are discussed herein for reusing hardware for encryption and authentication, where the hardware has a fixed input bandwidth, and where the hardware has the same bandwidth for a different input bandwidth. In order to accomplish this mechanism, systems and methods are provided herein for processing invalid data that appears within streams of valid data. Systems and methods are also provided herein for authentication mechanisms that require more than one data cycle to…
Circuit design instrumentation for state visualization
Granted: August 28, 2018
Patent Number:
10061879
An integrated circuit includes user storage circuits, a local control circuit, and scan storage circuits arranged in a scan chain. At least a portion of a design-under-test is implemented in a subset of the integrated circuit that comprises the user storage circuits. The local control circuit retrieves data stored in the user storage circuits through the scan storage circuits without erasing the data stored in the user storage circuits after halting oscillations in a user clock signal…
Variable precision floating-point adder and subtractor
Granted: August 21, 2018
Patent Number:
10055195
An integrated circuit may include a floating-point adder that supports variable precisions. The floating-point adder may receive first and second inputs to be added, where the first and second inputs each have a mantissa and an exponent. The mantissa and exponent values may be split into a near path and a far path using a dual path floating-point adder architecture depending on the difference of the exponents and on whether an addition or subtraction is being performed. The mantissa…
Dot product based processing elements
Granted: August 14, 2018
Patent Number:
10049082
Systems and methods for calculating a dot product using digital signal processing units that are organized into a dot product processing unit for dot product processing using multipliers and adders of the digital signal processing units.
Methods and apparatus for automated integrated circuit package testing
Granted: August 14, 2018
Patent Number:
10048306
A test system for testing an integrated circuit package is provided. The test system may include a test board on which a package under test can be mounted, a test box for gathering desired measurements on the package under test, and a test host for automatically controlling the test box during testing. The test box may be coupled to row multiplexing circuitry and column multiplexing circuitry for selectively addressing one or more daisy-chained nets in the package under test. The test…
Fixed-point and floating-point arithmetic operator circuits in specialized processing blocks
Granted: August 7, 2018
Patent Number:
10042606
The present embodiments relate to circuitry that efficiently performs floating-point arithmetic operations and fixed-point arithmetic operations. Such circuitry may be implemented in specialized processing blocks. If desired, the specialized processing blocks may include configurable interconnect circuitry to support a variety of different use modes. For example, the specialized processing block may efficiently perform a fixed-point or floating-point addition operation or a portion…
Variable precision floating-point multiplier
Granted: August 7, 2018
Patent Number:
10042607
Integrated circuits with specialized processing blocks are provided. The specialized processing blocks may include floating-point multiplier circuits that can be configured to support variable precision. A multiplier circuit may include a first carry-propagate adder (CPA), a second carry-propagate adder (CPA), and an associated rounding circuit. The first CPA may be wide enough to handle the required precision of the mantissa. In a bridged mode, the first CPA may borrow an additional bit…
