SYSTEMS AND METHODS FOR DIMENSIONING A LAND GRID ARRAY PAD
Granted: May 8, 2025
Application Number:
20250149428
A method for dimensioning a land grid array pad can include forming an initial landing area of a land grid array pad, wherein the initial landing area is dimensioned to cause at least a majority of a landing surface of one or more socket pins to land off of the initial landing area prior to actuation of one or more sockets including the one or more socket pins. The method can also include forming a final landing area of the land grid array pad, wherein the final landing area is…
Error Alert Encoding for Improved Error Mitigation
Granted: May 8, 2025
Application Number:
20250147844
Error alert encoding for improved error mitigation is described. In one or more implementations, a system includes a processor configured to receive an encoded signal indicating a type of an error detected in a memory, and output one or more mitigation commands to mitigate the type of the error detected in the memory based on the encoded signal. In one or more implementations, a memory system includes a memory and a buffer. The buffer is configured to output an encoded signal indicating…
MULTIPLEXED BUS STREAK MANAGEMENT
Granted: May 1, 2025
Application Number:
20250139022
A memory controller includes a command queue stage for storing decoded memory access requests, a first arbiter operable to select first decoded memory access requests for a first pseudo channel from the command queue stage, and a second arbiter operable to select second decoded memory access requests for a second pseudo channel from the command queue stage. Each of the first arbiter and the second arbiter is operable to select a first streak of a first type of accesses, and to change to…
STOCHASTIC ROUNDING CIRCUIT
Granted: April 24, 2025
Application Number:
20250130769
The disclosed circuit is configured to round a value in a first number format using a random value. Using the rounded value, the circuit can convert the rounded value to a second number format that has a lower precision than a precision of the first number format. Various other methods, systems, and computer-readable media are also disclosed.
FRAGMENTED TRANSFER OF DATA OVER NETWORKS
Granted: April 24, 2025
Application Number:
20250133133
Embodiments herein describe creating multiple packet fragments from a large data chunk that, for example, exceeds a maximum transmission unit (MTU) supported by a network. In one embodiment, a network interface controller or card (NIC) receives a direct memory access (DMA) from a connected host to transmit an IP packet or data using remote direct memory access (RDMA) technologies. The NIC can evaluate the data chunk associated with the DMA request and determine whether it exceeds the MTU…
Root-Trusted Guest Memory Page Management
Granted: April 24, 2025
Application Number:
20250130958
Root-trusted guest memory page management is described. A root-trusted guest is loaded by a hardware platform and authenticated. The root-trusted guest is configured to manage memory operations of different guests via special privileges that permit the root-trusted guest to execute memory operations using a guest's private memory page. To do so, a guest page table includes a novel “T-bit” in each entry, which indicates whether the root-trusted guest or a different guest owns the…
MULTIPLEXED-RANK DUAL INLINE MEMORY MODULE (MRDIMM) VIRTUAL CONTROLLER MODE
Granted: April 24, 2025
Application Number:
20250130936
A memory controller includes a command queue stage, an arbitration stage, and a dispatch queue. The command queue stage stores decoded memory access requests. The arbitration stage is operable to select first and second memory commands from the command queue stage for first and second pseudo-channels, respectively, using a shred resource. The dispatch queue has first and second upstream ports for receiving the first and second memory commands, and a downstream port for conducting first…
Security Framework for Virtual Machines
Granted: April 24, 2025
Application Number:
20250130844
A security framework for virtual machines is described. In one or more implementations, a hardware platform comprises physical computer hardware, the physical computer hardware including one or more processing units and one or more memories. The system also includes a virtual machine monitor configured to virtualize the physical computer hardware of the hardware platform to instantiate a plurality of framework-secure virtual machines. Further, the system includes a root framework-secure…
MULTI-FORMAT OPERAND CIRCUIT
Granted: April 24, 2025
Application Number:
20250130794
The disclosed processing circuit can perform an operation with a first operand having a first number format and a second operand having a second number format by directly using the first operand in the first number format and the second operand in the second number format to produce an output result. Various other methods, systems, and computer-readable media are also disclosed.
FLOATING POINT BIAS SWITCHING
Granted: April 24, 2025
Application Number:
20250130774
The disclosed circuit can interpret a bit sequence as a value based on one of multiple floating point number formats in a bias mode indicated by a bias mode indicator. The circuit can and perform an operation using the value in the bias mode. Various other methods, systems, and computer-readable media are also disclosed.
FLOATING-POINT CONVERSION CIRCUIT
Granted: April 24, 2025
Application Number:
20250130767
The disclosed circuit can select micro-operations specifically for converting a value in a first number format to a second number format. The circuit can include micro-operations for various conversions between different number formats, including number formats of different floating-point precisions. Various other methods, systems, and computer-readable media are also disclosed.
Transforming All-Bank Processing-in-Memory Operations into Multiple Masked Processing-in-Memory Operations
Granted: April 24, 2025
Application Number:
20250130715
A system includes memory hardware including a memory and a processing-in-memory component. A system includes a host including at least one core. A system includes a memory controller including a scheduling system. The scheduling system transforms an all-bank processing-in-memory command into multiple masked processing-in-memory commands. The scheduling system also schedules the multiple masked processing-in-memory commands to the processing-in-memory component.
SYSTEMS AND METHODS FOR SOFT FUSE OVERRIDE
Granted: April 10, 2025
Application Number:
20250117523
A method can include overriding settings of an integrated circuit device by reading one or more settings from a setting record that correspond to a part number of the integrated circuit device. The method can also include performing an override of the settings of the integrated circuit device based on the one or more settings of the setting record that correspond to the part number of the integrated circuit device. Various other methods and systems are also disclosed.
EFFICIENT BUS TURNAROUND FOR MEMORY CONTROLLER
Granted: April 3, 2025
Application Number:
20250110664
A memory controller includes a command queue for receiving memory access requests and an arbiter. The arbiter is operable to allow cross-mode activations during a streak of accesses of a current mode in response to a number of cross-mode accesses present in the command queue exceeding an adaptive threshold.
Fast Fourier Transforms for Processing-in-Memory
Granted: April 3, 2025
Application Number:
20250111006
Fast Fourier transforms for processing-in-memory are described. In accordance with the described techniques, a computing device includes a memory, a host processing unit, and a processing-in-memory unit that operates on data of one or more banks of the memory. The host processing unit stores interacting elements of a fast Fourier transform at locations in the one or more banks. The locations are mapped to a lane of the processing-in-memory unit. The host processing unit issues…
Method and Apparatus for Collaborative Memory Accesses
Granted: April 3, 2025
Application Number:
20250110898
Method and apparatus for collaborative memory accesses is described. A system includes a memory controller that receives a command from a host. The command is associated with at least one of a plurality of data elements. The memory controller causes execution of data casting operations that adjust a bit size of the plurality of data elements to generate casted data elements. The system includes an interface for communicating data between the host and a memory.
CONFIGURABLE CACHE REPLACEMENT
Granted: April 3, 2025
Application Number:
20250110895
The disclosed device includes a cache organized by sets and ways and a control circuit that selects a first way for a cache replacement from a first half of a set of ways. The control circuit also selects another way from a second half of the set of ways, and uses the second way for the cache replacement when the first way is unavailable. Various other methods, systems, and computer-readable media are also disclosed.
Scratchpad Memory Translation Lookaside Buffer
Granted: April 3, 2025
Application Number:
20250110894
Scratchpad memory translation lookaside buffer techniques are described. In an implementation, the techniques described herein relate to a device including a memory management unit implemented in hardware of an integrated circuit to receive a mapping instruction from a mapping instruction source, the mapping instruction specifying a mapping between a virtual memory address and a physical memory address of a scratchpad memory and store a virtual-to-physical mapping entry in a translation…
Preemptive Flushing of Processing-in-Memory Data Structures
Granted: April 3, 2025
Application Number:
20250110887
Preemptive flushing of data involved in executing a processing-in-memory command, from a cache system to main memory that is accessible by a processing-in-memory component, is described. In one example, a system includes an asynchronous flush controller that receives an indication of a subsequent processing-in-memory command to be executed as part of performing a computational task. While earlier commands of the computational task are executed, the asynchronous flush controller evicts or…
Speculative Cache Invalidation for Processing-in-Memory Instructions
Granted: April 3, 2025
Application Number:
20250110886
Speculative cache invalidation techniques for processing-in-memory instructions are described. In one example, a system includes a cache system including a plurality of cache levels and a cache coherence controller. The cache coherence controller is configured to perform a cache directory lookup using a cache directory. The cache directory lookup is configured to indicate whether data associated with a memory address specified by a processing-in-memory request is valid in memory. The…
