SYSTEMS AND METHODS FOR DRIVER CALIBRATION IN DIE-TO-DIE INTERFACES
Granted: March 13, 2025
Application Number:
20250088193
A method for driver calibration in die-to-die interfaces can include calibrating a delay lock loop of a delay line unit cell, by at least one processor, based on drive and load conditions of one or more driver unit cells of a physical layer of a die-to-die interconnect. The method can additionally include generating a clock signal, by the at least one processor, based on the delay lock loop. The method can further include communicating data, by the at least one processor, over the…
DIRECT-CONNECTED MACHINE LEARNING ACCELERATOR
Granted: March 13, 2025
Application Number:
20250086515
Techniques are disclosed for communicating between a machine learning accelerator and one or more processing cores. The techniques include obtaining data at the machine learning accelerator via an input/output die; processing the data at the machine learning accelerator to generate machine learning processing results; and exporting the machine learning processing results via the input/output die, wherein the input/output die is coupled to one or more processor chiplets via one or more…
PERFORMANCE AND MEMORY ACCESS TRACKING AND VISUALIZATION
Granted: March 6, 2025
Application Number:
20250077379
Techniques for performing memory operations are disclosed herein. The techniques include obtaining statistics for operation of a device, the statistics including either or both of performance statistics and memory access statistics; generating a plurality of visualizations of the statistics in one of an overlay mode or a scene annotation mode; and displaying the plurality of visualizations.
Mapping-Aware and Memory Topology-Aware Message Passing Interface Collectives
Granted: March 6, 2025
Application Number:
20250077320
A message passing interface processing system is described. In accordance with message passing logic, a node selects an affinity domain for communication of data associated with a message passing interface and selects a first rank of a first process of the message passing interface assigned to a first partition of the affinity domain as a first partition leader rank and an affinity domain leader rank. The node selects a second rank of a second process of the message passing interface…
Queue Management for Task Graphs
Granted: March 6, 2025
Application Number:
20250077307
In accordance with the described techniques, a command processor processes a fiber graph that includes fibers each having one or more tasks and indicates dependencies between the fibers and between tasks within the fibers. As part of this, the command processor dispatches a task from a fiber for execution by a processing element array based on the fiber being enqueued in a ready queue and the dependencies of the task being resolved. While the task is dispatched and unexecuted by the…
MEMORY CONTROLLER WITH PSEUDO-CHANNEL SUPPORT
Granted: February 20, 2025
Application Number:
20250061071
A data processor accesses a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent for generating a memory access request, a memory controller for providing a memory command to the memory in response to a normalized request selectively using a first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit, and a data fabric for converting the memory access request into the normalized request…
MULTIPLE MEMORY PERFORMANCE STATES USING SYSTEM MEMORY
Granted: February 6, 2025
Application Number:
20250044966
The disclosed device includes a cache that stores sets of settings for memory states, and registers that store a current set of settings for a memory. The device also includes a control circuit that can read, from the cache in response to the memory transitioning to a new memory state, a new set of settings corresponding to the new memory state, and write, to the plurality of registers, the new set of settings. Various other methods, systems, and computer-readable media are also…
MEMORY SELF-REFRESH POWER GATING
Granted: January 30, 2025
Application Number:
20250037750
The disclosed systems and methods include a control circuit for entering a low power state of a memory by preserving a context of the memory's controller and power gating the memory's physical layer. The context can be saved to a non-volatile memory device or by keeping a retention supply voltage to a register of the memory controller. Various other methods, systems, and computer-readable media are also disclosed.
ACTIVE HIBERNATE AND MANAGED MEMORY COOLING IN A NON-UNIFORM MEMORY ACCESS SYSTEM
Granted: January 30, 2025
Application Number:
20250036467
A method of operating a computing system includes storing a memory map identifying a first physical memory address as associated with a high performance memory and identifying a second physical memory address as associated with a low power consumption memory, servicing a first memory access request received from an application by accessing application data at the first physical memory address, in response to a change in one or more operating conditions of the computing system, moving the…
SYSTEMS AND METHODS FOR ABNORMAL POWER CONNECTION DETECTION
Granted: January 23, 2025
Application Number:
20250028010
A computer-implemented method for abnormal power connection detection can include receiving, by at least one processor, a power signal by a power connector and an additional power signal by an additional power connector. The method can additionally include performing, by the at least one processor, one or more measurements of the additional power signal. The method can also include carrying out, by the at least one processor, one or more response procedures based on the one or more…
HETEROGENEOUS CHIPLET POWER MANAGEMENT
Granted: January 2, 2025
Application Number:
20250004540
The disclosed device includes heterogeneous chiplets that can communicate when each of the heterogenous chiplets has locally reached an idle state. Once receiving confirmations of the idle state from each of the heterogenous chiplets, the chiplets can complete the entry of the low power state. Various other methods, systems, and computer-readable media are also disclosed.
LOAD DISTRIBUTION ACROSS MESH NETWORKS
Granted: January 2, 2025
Application Number:
20250007861
The disclosed device includes memory channel interfaces and mesh lanes each corresponding to a particular memory channel interface. The device also includes ports and various routing elements interconnecting the ports, mesh lanes, memory channel interfaces. The device further includes a control circuit configured to receive a data packet on a port, select a mesh lane based on a destination of the data packet, and forward the data packet to the selected mesh lane via a routing element.…
INTEGRATED CIRCUIT LOW CAPACITANCE ELECTROSTATIC DISCHARGE DIODES
Granted: January 2, 2025
Application Number:
20250006722
A semiconductor electrostatic discharge (ESD) protection circuit comprises an N diode for limiting negative going voltages with reference to ground (VSS) and a P diode for limiting positive going voltages with reference to a positive supply voltage (VDD). The N-diode is formed in a single P-well surrounded by an N-well ring. The P-diode is formed in a single N-well surrounded by a P-well ring. The N-diode comprises a plurality of N+ fingers, each N+ finger is surrounded by a P+ guard…
HOST-TO-DEVICE INTERFACE CIRCUITRY TESTING
Granted: January 2, 2025
Application Number:
20250006290
Some implementations provide systems methods and devices for integrated circuit self-test. The integrated circuit includes interface circuitry configured to read test data and to write the test data into memory of the integrated circuit. The integrated circuit also includes test circuitry configured to test the interface circuitry based on the test data written into memory of the integrated circuit. Some implementations provide an integrated circuit configured for storing and reading…
ANISOTROPIC SHADE SPACE SAMPLE DENSITY FOR DECOUPLED SHADING
Granted: January 2, 2025
Application Number:
20250005849
A technique for rendering is provided. The technique includes determining a first correspondence between a screen space and a shade space in a visibility pass; selecting a size for a shade space tile based on the correspondence between the screen space and the shade space; and shading the shade space tile based on the material texture correspondence.
SYSTEM AND METHOD FOR PRIMITIVE ID MAP SAMPLING
Granted: January 2, 2025
Application Number:
20250005841
A technique for sampling a primitive ID map. The technique includes identifying a sample point having a location in a texture space; obtaining a primitive ID sample from the primitive ID map based on the location of the sample point in the texture space; identifying a primitive based on the primitive ID; testing the location in the texture space for inclusion within the identified primitive; and selecting either the primitive ID or a different primitive ID based on the testing.
PRE-FILTERING WITH ANISOTROPIC FILTER IN DECOUPLED SHADING
Granted: January 2, 2025
Application Number:
20250005838
A technique for rendering is provided. The technique includes generating a first gradient for a shade space texture tile, wherein the first gradient reflects a relationship between shade space texel spacing and screen space pixel spacing; generating a second gradient for a shade space texel of the shade space texture tile, wherein the second gradient reflects a relationship between material texel spacing and shade space texel spacing; combining the first gradient and the second gradient…
Programmable Input/Output Dies for Specialization in Disaggregated Systems
Granted: January 2, 2025
Application Number:
20250004955
Programmable I/O die devices and methods are described. An example system includes an input/output die (IOD) that couples a plurality of devices. The system also includes a programmable fabric included in the IOD. The programmable fabric implements interconnects for connecting the plurality of devices according to a reconfigurable topology defined by a configuration of the programmable fabric.
LOW POWER MEMORY STATE DURING NON-IDLE PROCESSOR STATE
Granted: January 2, 2025
Application Number:
20250004652
The disclosed device includes multiple processing component, and a cache. One of the processing components can be instructed to avoid allocating to the cache and another of the processing components can be allowed use the cache while reducing accessing a memory. The memory can then enter a low power state in response to an idle state of the memory from the processing components avoiding accessing the memory for a period of time. Various other methods, systems, and computer-readable media…
MEMORY CONTROLLER WITH ENHANCED LOW-POWER STATE
Granted: January 2, 2025
Application Number:
20250004651
A memory accessing circuit includes a memory controller for scheduling accesses to a memory, and a physical interface circuit for driving signals to the memory according to scheduled accesses and having configuration data. The memory controller comprises a memory and is responsive to a low power mode entry signal to save the configuration data in the memory. The physical interface circuit removes operating power from circuitry in the physical interface circuit that stores the…
