DEVICE AND METHOD FOR ACCELERATING PHYSICS-BASED SIMULATIONS USING ARTIFICIAL INTELLIGENCE
Granted: January 2, 2025
Application Number:
20250005236
Method and devices are provided for performing a physics-based simulation. A processing devices comprises memory and a processor. The processor is configured to perform a physics-based simulation by executing a portion of the physics-based simulation, training a neural network model based on results from executing the first portion of the physics-based simulation, performing inference processing based on the results of the training of the neural network model and providing a prediction,…
SYSTEMS AND METHODS FOR SERVER LEVEL COOLING
Granted: January 2, 2025
Application Number:
20250008698
A method for server level cooling can include providing a printed circuit board and attaching a cooling system to the printed circuit board. The cooling system can be configured for placement thereon of two or more expansion cards having back side power delivery components. Various other methods, systems, and computer-readable media are also disclosed.
LOAD DISTRIBUTION ACROSS MESH NETWORKS
Granted: January 2, 2025
Application Number:
20250007861
The disclosed device includes memory channel interfaces and mesh lanes each corresponding to a particular memory channel interface. The device also includes ports and various routing elements interconnecting the ports, mesh lanes, memory channel interfaces. The device further includes a control circuit configured to receive a data packet on a port, select a mesh lane based on a destination of the data packet, and forward the data packet to the selected mesh lane via a routing element.…
INTEGRATED CIRCUIT LOW CAPACITANCE ELECTROSTATIC DISCHARGE DIODES
Granted: January 2, 2025
Application Number:
20250006722
A semiconductor electrostatic discharge (ESD) protection circuit comprises an N diode for limiting negative going voltages with reference to ground (VSS) and a P diode for limiting positive going voltages with reference to a positive supply voltage (VDD). The N-diode is formed in a single P-well surrounded by an N-well ring. The P-diode is formed in a single N-well surrounded by a P-well ring. The N-diode comprises a plurality of N+ fingers, each N+ finger is surrounded by a P+ guard…
HOST-TO-DEVICE INTERFACE CIRCUITRY TESTING
Granted: January 2, 2025
Application Number:
20250006290
Some implementations provide systems methods and devices for integrated circuit self-test. The integrated circuit includes interface circuitry configured to read test data and to write the test data into memory of the integrated circuit. The integrated circuit also includes test circuitry configured to test the interface circuitry based on the test data written into memory of the integrated circuit. Some implementations provide an integrated circuit configured for storing and reading…
ANISOTROPIC SHADE SPACE SAMPLE DENSITY FOR DECOUPLED SHADING
Granted: January 2, 2025
Application Number:
20250005849
A technique for rendering is provided. The technique includes determining a first correspondence between a screen space and a shade space in a visibility pass; selecting a size for a shade space tile based on the correspondence between the screen space and the shade space; and shading the shade space tile based on the material texture correspondence.
NEURAL NETWORK-BASED RAY TRACING
Granted: January 2, 2025
Application Number:
20250005842
A technique for performing ray tracing operations is provided. The technique includes traversing a bounding volume hierarchy for a ray to arrive at a bounding box without use of a neural network; perform a feature vector lookup using modified polar coordinates characterizing the ray relative to the bounding box to obtain a set of feature vectors; and obtaining output with the neural network using the set of feature vectors.
SYSTEM AND METHOD FOR PRIMITIVE ID MAP SAMPLING
Granted: January 2, 2025
Application Number:
20250005841
A technique for sampling a primitive ID map. The technique includes identifying a sample point having a location in a texture space; obtaining a primitive ID sample from the primitive ID map based on the location of the sample point in the texture space; identifying a primitive based on the primitive ID; testing the location in the texture space for inclusion within the identified primitive; and selecting either the primitive ID or a different primitive ID based on the testing.
SYSTEM AND METHOD FOR ADJUSTING FILTERING FOR TEXTURE STREAMING
Granted: January 2, 2025
Application Number:
20250005840
A technique for texture filtering. A transition is made from a first mipmap corresponding to a first texture resolution to a second mipmap corresponding to a second texture resolution. The first texture resolution is lower than the second texture resolution. As compared to standard trilinear filtering, initiation of the transition is delayed by an offset (or bias), which serves to delay the initial use of the second mipmap until it has been loaded. Following initiation of the transition,…
PRE-FILTERING WITH ANISOTROPIC FILTER IN DECOUPLED SHADING
Granted: January 2, 2025
Application Number:
20250005838
A technique for rendering is provided. The technique includes generating a first gradient for a shade space texture tile, wherein the first gradient reflects a relationship between shade space texel spacing and screen space pixel spacing; generating a second gradient for a shade space texel of the shade space texture tile, wherein the second gradient reflects a relationship between material texel spacing and shade space texel spacing; combining the first gradient and the second gradient…
Programmable Input/Output Dies for Specialization in Disaggregated Systems
Granted: January 2, 2025
Application Number:
20250004955
Programmable I/O die devices and methods are described. An example system includes an input/output die (IOD) that couples a plurality of devices. The system also includes a programmable fabric included in the IOD. The programmable fabric implements interconnects for connecting the plurality of devices according to a reconfigurable topology defined by a configuration of the programmable fabric.
RUNNING AVERAGE CACHE HIT RATE
Granted: January 2, 2025
Application Number:
20250004943
The disclosed device includes a first register that stores a cumulative delta value and a second register that stores an average cache hit rate. The device also includes a control circuit that calculates a cache hit rate and updates the cumulative delta value based on the cache hit rate and the average cache hit rate. The control circuit also updates the average cache hit rate based on the updated cumulative delta value, and can update a cache allocation policy based on the updated…
Scheduling Multiple Processing-in-Memory (PIM) Threads and Non-PIM Threads
Granted: January 2, 2025
Application Number:
20250004826
Scheduling requests of multiple processing-in-memory threads and requests of multiple non-processing-in-memory threads is described. In accordance with the described techniques, a memory controller receives a plurality of processing-in-memory threads and a plurality of non-processing-in-memory threads from a host. The memory controller schedules an order of execution for requests of the plurality of processing-in-memory threads and requests of the plurality of non-processing-in-memory…
Cross-Component Optimizing Compiler Systems
Granted: January 2, 2025
Application Number:
20250004731
Cross-component optimizing compiler systems are described. In accordance with the described techniques, machine learning models receive components of source code to be compiled. The machine learning models generate component prediction functions for the components of the source code. A tuning engine selects parameters for the components of the source code based on the component prediction functions. Domain-specific language compilers compile the source code based on the selected…
Selecting Intermediate Representation Transformations for Compilations
Granted: January 2, 2025
Application Number:
20250004730
Selecting intermediate representation transformation for compilations is described. In accordance with the described techniques, source code is received to be compiled by a compilation system for execution by a processor of hardware. Intermediate representation transformations are selected for the source code based on system load information associated with the hardware. The intermediate representation transformations are output to the compilation system.
LOW POWER MEMORY STATE DURING NON-IDLE PROCESSOR STATE
Granted: January 2, 2025
Application Number:
20250004652
The disclosed device includes multiple processing component, and a cache. One of the processing components can be instructed to avoid allocating to the cache and another of the processing components can be allowed use the cache while reducing accessing a memory. The memory can then enter a low power state in response to an idle state of the memory from the processing components avoiding accessing the memory for a period of time. Various other methods, systems, and computer-readable media…
MEMORY CONTROLLER WITH ENHANCED LOW-POWER STATE
Granted: January 2, 2025
Application Number:
20250004651
A memory accessing circuit includes a memory controller for scheduling accesses to a memory, and a physical interface circuit for driving signals to the memory according to scheduled accesses and having configuration data. The memory controller comprises a memory and is responsive to a low power mode entry signal to save the configuration data in the memory. The physical interface circuit removes operating power from circuitry in the physical interface circuit that stores the…
HETEROGENEOUS CHIPLET POWER MANAGEMENT
Granted: January 2, 2025
Application Number:
20250004540
The disclosed device includes heterogeneous chiplets that can communicate when each of the heterogenous chiplets has locally reached an idle state. Once receiving confirmations of the idle state from each of the heterogenous chiplets, the chiplets can complete the entry of the low power state. Various other methods, systems, and computer-readable media are also disclosed.
LIMITED BIT TOGGLING FOR DATA BUS INVERSION
Granted: January 2, 2025
Application Number:
20250004530
The disclosed device includes multiple data elements each configured to send a bit of a bit sequence by toggling at most half of a number of bits from a previously sent bit sequence. The bit sequence can first be biased and then XORed with the previously sent bit sequence. Various other methods, systems, and computer-readable media are also disclosed.
ALLOCATION CONTROL FOR CACHE
Granted: December 26, 2024
Application Number:
20240427704
A technique for operating a cache is disclosed. The technique includes based on a workload change, identifying a first allocation permissions policy; operating the cache according to the first allocation permissions policy; based on set sampling, identifying a second allocation permissions policy; and operating the cache according to the second allocation permissions policy.
