Selective Transfer of Cache Block Data
Granted: April 3, 2025
Application Number:
20250110884
Systems and techniques for selectively transferring one or more portions of a cache block in response to a request are described. Computing system components are informed as to instances where data transfer operations involve moving less than an entirety of data included in a cache block cache block. In one example, executable code for a computational task includes hints that identify when memory requests involve accessing and transmitting less than an entirety of a cache block and cause…
SYSTEMS AND METHODS FOR DATA INTERFACE CONNECTOR
Granted: April 3, 2025
Application Number:
20250112389
A data interface connector and method of manufacture and/or assembly thereof can include first electrical terminals at a first end of the data interface connector, the first electrical terminals being configured to interface with a mating data interface connector conforming to a first data interface specification. The data interface connector and method of manufacture and/or assembly thereof can include second electrical terminals at a second end of the data interface connector, the…
SPATIOTEMPORAL ADAPTIVE SHADING RATES FOR DECOUPLED SHADING
Granted: April 3, 2025
Application Number:
20250111601
A technique for rendering is provided. The technique includes performing a visibility pass that designates portions of shade space textures visible in a scene, wherein the visibility pass generates tiles that cover shade space textures visible in the scene; performing a rate controller operation on output of the visibility pass using spatiotemporal adaptive sampling; performing a shade space shading operation on the tiles that cover the shade space textures visible in the scene based on…
SPATIALLY ADAPTIVE SHADING RATES FOR DECOUPLED SHADING
Granted: April 3, 2025
Application Number:
20250111600
A technique for rendering is provided. The technique includes performing a visibility pass that designates portions of shade space textures visible in a scene, wherein the visibility pass generates tiles that cover shade space textures visible in the scene; performing a rate controller operation on output of the visibility pass using spatially-adaptive sampling; performing a sparse shade space shading operation on the tiles that cover the shade space textures visible in the scene based…
SIMPLIFIED LOW-PRECISION RAY INTERSECTION THROUGH ACCELERATED HIERARCHY STRUCTURE PRECOMPUTATION
Granted: April 3, 2025
Application Number:
20250111587
Devices and methods for rendering objects using ray tracing are provided which include during a build time: generating an accelerated hierarchy structure comprising data representing an approximate volume bounding a group of geometric shapes representing the objects in the scene and data representing the geometric shapes; and generating additional data used to transform rays, to be cast in the scene, from a high precision space to a low precision space; and during a render time occurring…
SINGLE MIP FILTERING WITH BANDWIDTH CONTROL
Granted: April 3, 2025
Application Number:
20250111582
A technique for rendering is provided. The technique includes determining a level of detail for a shade space texture and a screen space; shading the shade space texture having a resolution based on the level of detail; and for a reconstruction operation, performing sampling from the shade space texture, the sampling including a high frequency attenuation of samples of the shade space texture.
Fast Fourier Transforms for Processing-in-Memory
Granted: April 3, 2025
Application Number:
20250111006
Fast Fourier transforms for processing-in-memory are described. In accordance with the described techniques, a computing device includes a memory, a host processing unit, and a processing-in-memory unit that operates on data of one or more banks of the memory. The host processing unit stores interacting elements of a fast Fourier transform at locations in the one or more banks. The locations are mapped to a lane of the processing-in-memory unit. The host processing unit issues…
CONFIGURABLE CACHE REPLACEMENT
Granted: April 3, 2025
Application Number:
20250110895
The disclosed device includes a cache organized by sets and ways and a control circuit that selects a first way for a cache replacement from a first half of a set of ways. The control circuit also selects another way from a second half of the set of ways, and uses the second way for the cache replacement when the first way is unavailable. Various other methods, systems, and computer-readable media are also disclosed.
Scratchpad Memory Translation Lookaside Buffer
Granted: April 3, 2025
Application Number:
20250110894
Scratchpad memory translation lookaside buffer techniques are described. In an implementation, the techniques described herein relate to a device including a memory management unit implemented in hardware of an integrated circuit to receive a mapping instruction from a mapping instruction source, the mapping instruction specifying a mapping between a virtual memory address and a physical memory address of a scratchpad memory and store a virtual-to-physical mapping entry in a translation…
Speculative Cache Invalidation for Processing-in-Memory Instructions
Granted: April 3, 2025
Application Number:
20250110886
Speculative cache invalidation techniques for processing-in-memory instructions are described. In one example, a system includes a cache system including a plurality of cache levels and a cache coherence controller. The cache coherence controller is configured to perform a cache directory lookup using a cache directory. The cache directory lookup is configured to indicate whether data associated with a memory address specified by a processing-in-memory request is valid in memory. The…
Bypassing Cache Directory Lookups for Processing-in-Memory Instructions
Granted: April 3, 2025
Application Number:
20250110878
Selectively bypassing cache directory lookups for processing-in-memory instructions is described. In one example, a system maintains information describing a status—clean or dirty—of a memory address, where a dirty status indicates that the memory address is modified in a cache and thus different than the memory address as represented in system memory. A processing-in-memory request involving the memory address is assigned a cache directory bypass bit based on the status of the…
REMOTE ACCELERATION FOR DATA DEPENDENT ADDRESS CALCULATION
Granted: April 3, 2025
Application Number:
20250110877
The disclosed device includes a processor and an interconnect connecting the processor to a memory. The interconnect includes an interconnect agent that can forward memory requests from the processor to the memory and receive requested data returned by the memory. The requested data can include information for a next memory request such that the interconnect agent can send, to the memory, a speculative memory request using information for the next memory request that was received in…
Methods for Enhanced Memory Context Restore
Granted: April 3, 2025
Application Number:
20250110864
Enhanced methods for memory context restore are described. A device may include a physical layer (PHY) having an interface to support communication of command signals and data with a physical memory. The PHY implements a training mode to train the interface, detect values of a plurality of parameters as part of training the interface, and store the detected values as initial training data. The PHY also implements a retraining mode to use the initial training data as seed data to retrain…
Data Compression Using Reconfigurable Hardware based on Data Redundancy Patterns
Granted: April 3, 2025
Application Number:
20250110861
In accordance with the described techniques for data compression using reconfigurable hardware based on data redundancy patterns, a computing device includes a memory, processing-in-memory units, a host processing unit, and a compression unit having reconfigurable logic for performing multiple compression algorithms. The host processing unit issues processing-in-memory requests instructing the processing-in-memory units to scan a block of the memory for one or more data redundancy…
ARBITRATED INTERRUPT STEERING IN HETEROGENEOUS PROCESSORS
Granted: April 3, 2025
Application Number:
20250110773
The disclosed device includes a heterogeneous processor architecture having heterogeneous processors, and a control circuit that can assign, in response to an interrupt, the interrupt to one of the heterogenous processors that is selected based on power efficiency. Various other methods, systems, and computer-readable media are also disclosed.
TESTING MULTI-CYCLE PATHS BASED ON CLOCK PATTERN
Granted: March 27, 2025
Application Number:
20250102570
A disclosed technique includes based on a clock pattern, determining an enable configuration for setting enable signals for one or more multi-cycle paths of a hardware logic network; controlling a selector to set the enable configuration for the one or more multi-cycle paths; and executing testing operations for the hardware logic network with the one or more multi-cycle paths enabled according to the enable configuration.
SYSTEMS AND METHODS FOR DYNAMIC RESOURCE MANAGEMENT
Granted: March 27, 2025
Application Number:
20250103395
A computer-implemented method for dynamic resource management can include evaluating, by at least one processor, whether a priority of one or more processes associated with a request for one or more shared resources meets a threshold condition. The method can additionally include determining, by the at least one processor and in response to an evaluation that the priority meets the threshold condition, whether the one or more shared resources is available to meet the request. The method…
SYSTEMS AND METHODS FOR IMPLEMENTING FINE-GRAIN SINGLE ROOT INPUT/OUTPUT (I/O) VIRTUALIZATION (SR-IOV)
Granted: March 27, 2025
Application Number:
20250103371
The disclosed computing device can include host circuitry configured to provide a physical function and guest circuitry configured to provide a virtual function. The host circuitry is configured to dynamically assign request identifiers for accessing at least the host circuitry in a manner that allows the request identifiers to change on a command-to-command basis instead of a time-to-time basis that uses fixed value request identifiers in time slices. Various other methods, systems, and…
EXTENDING SYNCHRONOUS CIRCUIT DESIGNS OVER ASYNCHRONOUS COMMUNICATION LINKS UTILIZING A TRANSACTOR-BASED FRAMEWORK
Granted: March 27, 2025
Application Number:
20250103360
A circuit design emulation system having a plurality of integrated circuits (ICs) includes a first IC. The first IC includes an originator circuit configured to issue a request of a transaction directed to a completer circuit. The request is specified in a communication protocol. The first IC includes a completer transactor circuit coupled to the originator circuit and configured to translate the request into request data. The first IC includes a first interface circuit configured to…
METHOD AND APPARATUS FOR ENABLING MIMD-LIKE EXECUTION FLOW ON SIMD PROCESSING ARRAY SYSTEMS
Granted: March 27, 2025
Application Number:
20250103342
A method, apparatus and computer readable medium that use of a lightweight finite state machine (FSM) control flow block to enable limited execution of data-dependent control flow, thereby enhancing the control flow flexibility of array scale SIMD processors. In certain cases, the FSM block contains registers responsible for decoding and managing single global instructions into multiple local instructions that can incorporate data-dependent control flow.
