REDUCING SYSTEM POWER CONSUMPTION WHEN CAPTURING DATA FROM A USB DEVICE
Granted: November 30, 2023
Application Number:
20230384855
Systems and methods are disclosed for reducing power consumed by capturing data from an I/O device. Techniques disclosed include receiving descriptors, by a controller of an I/O host of a system, including information associated with respective data chunks to be captured from an I/O device buffer of the I/O device. Techniques disclosed further include capturing, based on the descriptors, the data chunks. The capturing comprises pulling the data chunks from the I/O device buffer at a…
PIPELINE DELAY ELIMINATION WITH PARALLEL TWO LEVEL PRIMITIVE BATCH BINNING
Granted: November 23, 2023
Application Number:
20230377086
A technique for rendering is provided. The technique includes for a set of primitives processed in a coarse binning pass, outputting early draw data to an early draw buffer; while processing the set of primitives in the coarse binning pass, processing the early draw data in a fine binning pass; and processing remaining primitives of the set of primitives in the fine binning pass.
Method And Apparatus For a Page-Local Delta-Based Prefetcher
Granted: November 23, 2023
Application Number:
20230376420
A method includes recording a first set of consecutive memory access deltas, where each of the consecutive memory access deltas represents a difference between two memory addresses accessed by an application, updating values in a prefetch training table based on the first set of memory access deltas, and predicting one or more memory addresses for prefetching responsive to a second set of consecutive memory access deltas and based on values in the prefetch training table.
MEMORY CALIBRATION SYSTEM AND METHOD
Granted: November 16, 2023
Application Number:
20230368832
A method for performing stutter of dynamic random access memory (DRAM) where a system on a chip (SOC) initiates bursts of requests to the DRAM to fill buffers to allow the DRAM to self-refresh is disclosed. The method includes issuing, by a system management unit (SMU), a ForceZQCal command to the memory controller to initiate the stutter procedure in response to receiving a timeout request, such as an SMU ZQCal timeout request, periodically issuing a power platform threshold (PPT)…
Real Time Profile Switching for Memory Overclocking
Granted: November 2, 2023
Application Number:
20230350591
Profile switching for memory overclocking is described. In accordance with the described techniques, a memory is operated according to a first memory profile. During operation of the memory according to the first memory profile, a request is received to operate the memory according to a second memory profile. Responsive to the request, operation of the memory is switched to operate according to the second memory profile without rebooting. In one or more implementations, at least one of…
METHOD AND APPARATUS FOR PERFORMING HIGH SPEED PARALLEL LOCALLY ORDER CLUSTERING FOR A BOUNDING VOLUME HIERARCHY
Granted: November 2, 2023
Application Number:
20230351667
A technique for building a bounding volume hierarchy is disclosed. The technique includes performing a nearest neighbor search for a set of clusters to generate a set of nearest neighbors; without performing a global barrier operation, performing a merge operation for the set of clusters, based on the set of nearest neighbors to generate merge results for the set of clusters; and without performing a global barrier operation, outputting clusters for a level of the bounding volume…
ACCELERATING NEURAL NETWORKS WITH ONE SHOT SKIP LAYER PRUNING
Granted: November 2, 2023
Application Number:
20230351187
Systems, methods, and devices for pruning a convolutional neural network (CNN). A subset of layers of the CNN is chosen, and for each layer of the subset of layers, how salient each filter in the layer is to an output of the CNN is determined, a subset of the filters in the layer is determined based on the salience of each filter in the layer, and the subset of filters in the layer is pruned. In some implementations, the layers of the subset of layers of the CNN are non-contiguous. In…
METHOD AND APPARATUS OF INTEGRATING MEMORY STACKS
Granted: November 2, 2023
Application Number:
20230350830
An apparatus and method for performing memory operations in memory stacks comprising receiving a memory operation request at a first memory controller, where the first memory controller is in included in a first logic die in communication with a first memory die of a first memory technology, from a processor via a first bus. The method further comprising, on a condition that the memory operation request is associated with a second memory technology, communicating the memory operation…
Identifying Memory System Sensitivity to Timing Parameters
Granted: November 2, 2023
Application Number:
20230350715
Various timing parameter values for a memory system are changed and a workload is run using the changed timing parameter values resulting in workload performance values. The workload is run multiple times with different timing parameter values and the performance values generated by the workload are used to generate and output a performance indication that identifies how sensitive performance of the physical memory is to the one or more timing parameters. The parameter values generated…
Real Time Workload-Based System Adjustment
Granted: November 2, 2023
Application Number:
20230350696
Real time workload-based system adjustment is described. In accordance with the described techniques, a processor and a memory are operated according to first settings associated with a first workload. A second workload configured to utilize the processor and the memory is detected. The second workload is associated with second settings. Responsive to detecting the second workload, operation of the processor and the memory are adjusted to operate according to the second settings without…
COMPILER DIRECTED FINE GRAINED POWER MANAGEMENT
Granted: November 2, 2023
Application Number:
20230350485
Systems, methods, devices, and computer-implemented instructions for processor power management implemented in a compiler. In some implementations, a characteristic of code is determined. An instruction based on the determined characteristic is inserted into the code. The code and inserted instruction are compiled to generate compiled code. The compiled code is output.
DEVICE AND METHOD FOR EFFICIENT TRANSITIONING TO AND FROM REDUCED POWER STATE
Granted: November 2, 2023
Application Number:
20230350484
A processing device and method for efficient transitioning to and from a reduced power state is provided. The processing device comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the plurality of components. The power management controller receives an indication that the plurality of components are idle, executes a process to enter a component into a reduced power state in response…
PLATFORM POWER MANAGER FOR RACK LEVEL POWER AND THERMAL CONSTRAINTS
Granted: November 2, 2023
Application Number:
20230350480
Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or…
ALTERNATIVE PROTOCOL OVER PHYSICAL LAYER
Granted: October 26, 2023
Application Number:
20230342325
A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a non-PCIe protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol…
DYNAMIC CACHE BYPASS FOR POWER SAVINGS
Granted: October 26, 2023
Application Number:
20230341922
A technique for operating a cache is disclosed. The technique includes in response to a power down trigger that indicates that the cache effectiveness is considered to be low, powering down the cache.
MEMORY ENCRYPTION
Granted: October 12, 2023
Application Number:
20230325326
A memory controller includes encryption circuits for encrypting write data to be written to an address in a RAM memory. A tweak value is provided based at least on the address. The tweak value is encrypted with Advanced Encryption Standard (AES) encryption using a first key. A first block write data is encrypted by manipulating it based on the encrypted tweak value, AES encrypting with a second key, and then manipulating the result based on the encrypted tweak value again. For subsequent…
SUPPRESSING CACHE LINE MODIFICATION
Granted: October 12, 2023
Application Number:
20230325313
Disclosed is a system and method for use in a cache for suppressing modification of cache line. The system and method includes a processor and a memory operating cooperatively with a cache controller. The memory includes a coherence directory stored within a cache created to track at least one cache line in the cache via the cache controller. The processor instructs a cache controller to store a first data in a cache line in the cache. The cache controller tags the cache line based on…
Lid Carveouts for Processor Lighting
Granted: October 12, 2023
Application Number:
20230324967
Package lids with carveouts configured to expose lights directly connected to an internal component of a processor are described. Lid carveouts are configured to precisely align and mechanically secure a cooling device to the package lid by receiving protrusions of the cooling device via a press fit connection, while maintaining visibility of lights directly connected to processor internal components when the cooling device is connected. Lid carveouts are further configured to expose one…
User Configurable Hardware Settings for Overclocking
Granted: October 12, 2023
Application Number:
20230324947
User configurable hardware settings for overclocking is described. In accordance with the described techniques, user input to adjust hardware settings for operating a processing unit in an overclocking mode is received. The user input, for example, adjusts at least one of a voltage droop threshold or a frequency adjustment of the clock rate. A voltage droop is detected while operating the processing unit in the overclocking mode. Responsive to detecting the voltage droop, a clock rate of…
Core Activation and Deactivation for a Multi-Core Processor
Granted: October 5, 2023
Application Number:
20230315191
Core activation and deactivation for a multi-core processor is described. In accordance with the described techniques, a processor having multiple cores operates using a first core configuration. A request to switch from the first core configuration to a second core configuration is received. Responsive to the request, a switch from the first core configuration to the second core configuration occurs by adjusting a number of active cores of the processor without rebooting.
