Page Swapping To Protect Memory Devices
Granted: October 5, 2023
Application Number:
20230315320
A page swapping memory protection system tracks accesses to physical memory pages, such as in a table with each row storing a physical memory page address and a counter value. This counter value records the number of accesses (e.g., read access or write accesses) to the corresponding physical memory page. In response to one of the counters exceeding a threshold value, the corresponding physical memory page is swapped with another page in physical memory (e.g., a page the table indicates…
Core Activation and Deactivation for a Multi-Core Processor
Granted: October 5, 2023
Application Number:
20230315191
Core activation and deactivation for a multi-core processor is described. In accordance with the described techniques, a processor having multiple cores operates using a first core configuration. A request to switch from the first core configuration to a second core configuration is received. Responsive to the request, a switch from the first core configuration to the second core configuration occurs by adjusting a number of active cores of the processor without rebooting.
USING A HARDWARE-BASED CONTROLLER FOR POWER STATE MANAGEMENT
Granted: October 5, 2023
Application Number:
20230315188
Methods and systems are disclosed for transitioning, by a hardware-based controller, a system on a chip (SoC) into different power states. Techniques disclosed include tracking, by the controller, metrics associated with the SoC and transitioning, by the controller, the SoC from a first power state to a second power state based on the tracked metrics. Were the total amount of power that is used by at least a portion of the transition between the first power state to the second power…
Lid Carveouts for Processor Connection and Alignment
Granted: October 5, 2023
Application Number:
20230315171
Package lids with carveouts configured for processor connection and alignment are described. Lid carveouts are configured to align and mechanically secure a cooling device to the package lid by receiving protrusions of the cooling device. Because the lid carveouts ensure precise alignment and orientation of a cooling device relative to a package lid, the lid design enables targeted cooling of discrete portions of the lid. Lid carveouts are further configured to expose one or more…
Array of Pointers Prefetching
Granted: September 28, 2023
Application Number:
20230305849
Array of pointers prefetching is described. In accordance with described techniques, a pointer target instruction is detected by identifying that a destination location of a load instruction is used in an address compute for a memory operation and the load instruction is included in a sequence of load instructions having addresses separated by a step size. An instruction for fetching data of a future load instruction is injected in an instruction stream of a processor. The data of the…
ELECTRONIC DEVICE INCLUDING DIES AND AN INTERCONNECT COUPLED TO THE DIES AND PROCESSES OF FORMING THE SAME
Granted: September 28, 2023
Application Number:
20230307405
An electronic device can include a first die, a second die, and an interconnect. The first die or the second die has a principal function as a power module or a memory. The first die includes a first bond pad, and the second die includes a second bond pad. The device sides of the first and second dies are along the same sides as the first and second bond pads. In an embodiment, the first die and the second die are in a chip first, die face-up configuration. The first and the second bond…
Error-Tolerant Memory System for Machine Learning Systems
Granted: September 28, 2023
Application Number:
20230305923
A memory system uses error detection codes to detect when errors have occurred in a region of memory. A count of the number of errors is kept and a notification is output in response to the number of errors satisfying a threshold value. The notification is an indication to a host (e.g., a program accessing or managing a machine learning system) that the threshold number of errors have been detected in the region of memory. As long as the number of errors that have been detected in the…
Load Dependent Branch Prediction
Granted: September 21, 2023
Application Number:
20230297381
Load dependent branch prediction is described. In accordance with described techniques, a load dependent branch instruction is detected by identifying that a destination location of a load instruction is used in an operation for determining whether a conditional branch is taken or not taken. The load instruction is included in a sequence of load instructions having addresses separated by a step size. An instruction is injected in an instruction stream of a processor for fetching data of…
Load Dependent Branch Prediction
Granted: September 21, 2023
Application Number:
20230297381
Load dependent branch prediction is described. In accordance with described techniques, a load dependent branch instruction is detected by identifying that a destination location of a load instruction is used in an operation for determining whether a conditional branch is taken or not taken. The load instruction is included in a sequence of load instructions having addresses separated by a step size. An instruction is injected in an instruction stream of a processor for fetching data of…
STACK-BASED RAY TRAVERSAL WITH DYNAMIC MULTIPLE-NODE ITERATIONS
Granted: September 21, 2023
Application Number:
20230298256
A technique for performing ray tracing operations is provided. The technique includes, in response to detecting that a threshold number of traversal stage work-items of a wavefront have terminated, increasing intersection test parallelization for non-terminated work-items.
DISTRIBUTED VISIBILITY STREAM GENERATION FOR COARSE GRAIN BINNING
Granted: September 21, 2023
Application Number:
20230298261
Techniques for performing rendering operations are disclosed herein. The techniques include performing two-level primitive batch binning in parallel across multiple rendering engines, wherein tiles for subdividing coarse-level work across the rendering engines have the same size as tiles for performing coarse binning.
GRAPHICS LIBRARY EXTENSIONS
Granted: September 14, 2023
Application Number:
20230290035
A system and method for performing graphics processing is provided. The system and method includes processing an allocation command for a buffer object; reserving processor address space for a data store of the buffer object with uncommitted physical memory in response to the allocation command including a null parameter, and reserving processor address space for a data store of the buffer object with committed physical memory in response to the allocation command including a non-null…
EFFICIENT AND LOW POWER REFERENCE VOLTAGE MIXING
Granted: September 14, 2023
Application Number:
20230290400
A data transmission system includes a first integrated circuit. The first integrated circuit includes a first mixing terminal coupled to a first power supply voltage terminal at a point internal to the first integrated circuit, a first return terminal, a first resistor having a first terminal coupled to the first mixing terminal, and a second terminal for providing a first mixed voltage, and a second resistor having a first terminal coupled to the second terminal of the first resistor,…
Cache Grouping for Increasing Performance and Fairness in Shared Caches
Granted: September 14, 2023
Application Number:
20230289290
A method includes monitoring one or more metrics for each of a plurality of cache users sharing a cache, and assigning each of the plurality of cache users to one of a plurality of groups based on the monitored one or more metrics.
EFFICIENT MEMORY-SEMANTIC NETWORKING USING SCOPED MEMORY MODELS
Granted: September 14, 2023
Application Number:
20230289070
A framework disclosed herein extends a relaxed, scoped memory model to a system that includes nodes across a commodity network and maintains coherency across the system. A new scope, cluster scope, is defined, that allows for memory accesses at scopes less than cluster scope to operate on locally cached versions of remote data from across the commodity network without having to issue expensive network operations. Cluster scope operations generate network commands that are used to…
MEMORY ORGANIZATION FOR MULTI-MODE SUPPORT
Granted: September 7, 2023
Application Number:
20230280906
A memory package includes first, second, third, and fourth channels arranged consecutively in a clockwise direction on the memory package, each of the first, second, third, and fourth channels having access circuitry and memory arrays. In a first mode, the first channel controls access to the memory arrays in the second channel and the fourth channel controls access to the memory arrays in the third channel.
TECHNIQUE FOR EXTENDED IDLE DURATION FOR DISPLAY TO IMPROVE POWER CONSUMPTION
Granted: September 7, 2023
Application Number:
20230280819
A method and system for operating in a single display mode operation and a dual pipe mode of operation is disclosed. The method and system includes operating in a dual pipe mode of operation in which each display pipe transmits data from a respective buffer to an associated display. The method and system further includes operating in a single display mode of operation in which one display pipe transmits data from a plurality of buffers to an associated display.
WAVEFRONT SELECTION AND EXECUTION
Granted: August 24, 2023
Application Number:
20230266975
Techniques are provided for executing wavefronts. The techniques include at a first time for issuing instructions for execution, performing first identifying, including identifying that sufficient processing resources exist to execute a first set of instructions together within a processing lane; in response to the first identifying, executing the first set of instructions together; at a second time for issuing instructions for execution, performing second identifying, including…
VRS RATE FEEDBACK
Granted: August 10, 2023
Application Number:
20230252713
Techniques for performing shader operations are provided. The techniques include, performing pixel shading at a shading rate defined by pixel shader variable rate shading (“VRS”) data, and updating the pixel VRS data that indicates one or more shading rates for one or more tiles based on whether the tiles of the one or more tiles include triangle edges or do not include triangle edges, to generate updated VRS data.
DEVICE AND METHOD FOR ACCELERATING MATRIX MULTIPLY OPERATIONS
Granted: August 3, 2023
Application Number:
20230244751
A processing device is provided which comprises memory configured to store data and a plurality of processor cores in communication with each other via first and second hierarchical communication links. Processor cores of a first hierarchical processor core group are in communication with each other via the first hierarchical communication links and are configured to store, in the memory, a sub-portion of data of a first matrix and a sub-portion of data of a second matrix. The processor…
