METHOD AND SYSTEM FOR INTEGRATING COMPRESSION
Granted: June 15, 2023
Application Number:
20230186523
A method and apparatus for integrating data compression in a computer system includes receiving first data at a first system level. Based upon a number of planes of the first data being less than or equal to a threshold, the data is compressed with a first data compression scheme, and transferred to a second system level for processing. Based upon the number of planes of the first data exceeding the threshold, the first data is transferred uncompressed to the second system level for…
Alleviating Interconnect Traffic in a Disaggregated Memory System
Granted: June 15, 2023
Application Number:
20230185478
One or both of read and write accesses to a fabric-attached memory module via a fabric interconnect are monitored. In one or more implementations, offloading of one or more tasks accessing the fabric-attached memory module to a processor of a routing system associated with the fabric-attached memory module is initiated based on the read and write accesses to the fabric-attached memory module. Additionally or alternatively, replicating memory of the fabric-attached memory module to a…
VLIW Power Management
Granted: June 15, 2023
Application Number:
20230185575
VLIW directed Power Management is described. In accordance with described techniques, a program is compiled to generate instructions for execution by a very long instruction word machine. During the compiling, power configurations for the very long instruction word machine to execute the instructions are determined, and fields of the instructions are populated with the power configurations. In one or more implementations, an instruction that includes a power configuration for the very…
METHOD OF TASK TRANSITION BETWEEN HETEROGENOUS PROCESSORS
Granted: June 15, 2023
Application Number:
20230185623
A method, system, and apparatus determines whether a task should be relocated from a first processor to a second processor by comparing performance metrics to associated thresholds or by using other indications. The task is relocated from the first processor to the second processor and executed on the second processor based on the com paring.
DEVICE AND METHOD FOR IMAGE DEMOSAICING
Granted: June 15, 2023
Application Number:
20230186427
A method and processing device for image demosaicing is provided. The processing device comprises memory and a processor. The processor is configured to, for a pixel of a Bayer image which filters an acquired image using three color components, determine directional color difference weightings in a horizontal direction and a vertical direction, determine a color difference between the first color component and the second color component and a color difference between the second color…
READ CLOCK START AND STOP FOR SYNCHRONOUS MEMORIES
Granted: June 8, 2023
Application Number:
20230178138
A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The mode register provides the read clock mode signal in response to a read clock mode, wherein the read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously when the read clock mode is a first mode, and as a strobe signal that is active…
READ CLOCK TOGGLE AT CONFIGURABLE PAM LEVELS
Granted: June 8, 2023
Application Number:
20230178126
A read clock circuit selectively provides a read clock signal from a memory to a memory controller over a memory bus. A pulse-amplitude modulation (PAM) driver including an input and an output capable of driving at least three levels indicating respective digital values. A digital control circuit is coupled to the PAM driver and operable to cause the PAM driver to provide a preamble signal before the read clock signal, the preamble signal including an initial toggling state in which the…
HIGH-BANDWIDTH MEMORY MODULE ARCHITECTURE
Granted: June 8, 2023
Application Number:
20230178121
A high-bandwidth dual-inline memory module (HB-DIMM) includes a plurality of memory chips, a plurality of data buffer chips, and a register clock driver (RCD) circuit. The data buffer chips are coupled to respective sets of the memory chips and transmit data from the memory chips over a host bus at a data rate twice that of the memory chips. The RCD circuit includes a host bus interface and a memory interface coupled to the plurality of memory chips. The RCD circuit implements commands…
Shader Source Code Performance Prediction
Granted: June 8, 2023
Application Number:
20230176847
Shader source code performance prediction is described. In accordance with the described techniques, an update to shader source code for implementing a shader is received. A prediction of performance of the shader on a processing unit is generated based on the update to the shader source code. Feedback about the update is output. The feedback includes the prediction of performance of the shader. In one or more implementations, generating the prediction of performance of the shader…
READ CLOCK START AND STOP FOR SYNCHRONOUS MEMORIES
Granted: June 8, 2023
Application Number:
20230176786
A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The mode register provides the read clock mode signal in response to a read clock mode, wherein the read clock circuit provides the hybrid read clock signal as a…
READ CLOCK START AND STOP FOR SYNCHRONOUS MEMORIES
Granted: June 8, 2023
Application Number:
20230176608
A memory includes a read clock state machine and a read clock driver circuit. The read clock state machine has a first input for receiving a read command signal, a second input for receiving a read clock mode signal, and an output for providing a drive enable signal. The read clock driver circuit has an output for providing a read clock signal in response to a clock signal when the drive enable signal is active. When the read clock mode signal indicates a read-only mode, the read clock…
COMPRESSION AWARE PREFETCH
Granted: June 1, 2023
Application Number:
20230169007
Methods, devices, and systems for prefetching data. First data is loaded from a first memory location. The first data in cached in a cache memory. Other data is prefetched to the cache memory based on a compression of the first data and a compression of the other data. In some implementations, the compression of the first data and the compression of the other data are determined based on metadata associated with the first data and metadata associated with the other data. In some…
LOW LATENCY WIRELESS VIRTUAL REALITY SYSTEMS AND METHODS
Granted: May 18, 2023
Application Number:
20230156250
Virtual Reality (VR) processing devices and methods are provided for transmitting user feedback information comprising at least one of user position information and user orientation information, receiving encoded audio-video (AN) data, which is generated based on the transmitted user feedback information, separating the A/V data into video data and audio data corresponding to a portion of a next frame of a sequence of frames of the video data to be displayed, decoding the portion of a…
PERFORMANCE MANAGEMENT DURING POWER SUPPLY VOLTAGE DROOP
Granted: May 11, 2023
Application Number:
20230144770
A method for controlling a data processing system includes detecting a droop in a power supply voltage of a functional circuit of the data processing system greater than a programmable droop threshold. An operation of the data processing system is throttled according to a programmable step size, a programmable assertion time, and a programmable de-assertion time in response to detecting the droop.
COMPENSATION METHODS FOR VOLTAGE AND TEMPERATURE (VT) DRIFT OF MEMORY INTERFACES
Granted: May 11, 2023
Application Number:
20230141595
A data processing system includes a data processor coupled to a memory. The data processor includes a reference clock generation circuit for providing a reference clock signal, a first delay circuit for delaying the reference clock signal by a first amount to provide a command and address signal, a second delay circuit for delaying the reference clock signal by a second amount to provide a read data signal, a calibration circuit for determining current values of the first and second…
ERROR PIN TRAINING WITH GRAPHICS DDR MEMORY
Granted: May 11, 2023
Application Number:
20230146703
A receiver is trained for receiving a signal over a data bus. A volatile memory is commanded over the data bus to place a selected pulse-amplitude modulation (PAM) driver in a mode with a designated steady output level. At a receiver circuit coupled to the selected PAM driver, a respective reference voltage associated with the designated steady output level is swept through a range of voltages and the respective reference voltage is compared to a voltage received from the PAM driver to…
SECURE TESTING MODE
Granted: May 11, 2023
Application Number:
20230146154
A technique for operating a processing device is disclosed. The method includes irreversibly activating a testing mode switch of the processing device; in response to the activating, entering a testing mode in which normal operation of the processing device is disabled; receiving software for the processing device in the testing mode; based on whether the software is verified as testing mode-signed software, executing or not executing the software.
REDUCING LATENCY IN HIGHLY SCALABLE HPC APPLICATIONS VIA ACCELERATOR-RESIDENT RUNTIME MANAGEMENT
Granted: May 11, 2023
Application Number:
20230145253
Methods and systems for runtime management by an accelerator-resident manager. Techniques include receiving, by the manager, a representation of a processing flow of an application, including a plurality of kernels and respective dependencies. The manager, then, assigns the plurality of kernels to one or more APUs managed it and launches the plurality of kernels on their assigned APUs to run in an iteration according to the respective dependencies.
PERFORMANCE MANAGEMENT DURING POWER SUPPLY VOLTAGE DROOP
Granted: May 11, 2023
Application Number:
20230144770
A method for controlling a data processing system includes detecting a droop in a power supply voltage of a functional circuit of the data processing system greater than a programmable droop threshold. An operation of the data processing system is throttled according to a programmable step size, a programmable assertion time, and a programmable de-assertion time in response to detecting the droop.
COMPENSATION METHODS FOR VOLTAGE AND TEMPERATURE (VT) DRIFT OF MEMORY INTERFACES
Granted: May 11, 2023
Application Number:
20230141595
A data processing system includes a data processor coupled to a memory. The data processor includes a reference clock generation circuit for providing a reference clock signal, a first delay circuit for delaying the reference clock signal by a first amount to provide a command and address signal, a second delay circuit for delaying the reference clock signal by a second amount to provide a read data signal, a calibration circuit for determining current values of the first and second…
