FLEXIBLE MEMORY SYSTEM
Granted: June 29, 2023
Application Number:
20230205420
A technique for operating a memory system is disclosed. The technique includes performing a first request, by a first memory client, to access data at a first memory address, wherein the first memory address refers to data in a first memory section that is coupled to the first memory client via a direct memory connection; servicing the first request via the direct memory connection; performing a second request, by the first client, to access data at a second memory address, wherein the…
METHOD AND APPARATUS FOR MANAGING POWER STATES
Granted: June 29, 2023
Application Number:
20230205297
A method and apparatus for managing power states in a computer system includes, responsive to an event received by a processor, powering up a first circuitry. Responsive to the event not being serviceable by the first circuitry, powering up at least a second circuitry of the computer system to service the event.
MULTI-CHIPLET CLOCK DELAY COMPENSATION
Granted: June 29, 2023
Application Number:
20230205252
Methods and systems are disclosed for clock delay compensation in a multiple chiplet system. Techniques disclosed include distributing, by a clock generator, a clock signal across distribution trees of respective chiplets; measuring phases, by phase detectors, where each phase measurement is associated with a chiplet of the chiplets and is indicative of a propagation speed of the clock signal through the distribution tree of the chiplet. Then, for each chiplet, techniques are further…
LOW POWER CACHE
Granted: June 22, 2023
Application Number:
20230195642
A cache includes an upstream port, a cache memory for storing cache lines each having a line width, and a cache controller. The cache controller is coupled to the upstream port and the cache memory. The upstream port transfers data words having a transfer width less than the line width. In response to a cache line fill, the cache controller selectively determines data bus inversion information for a sequence of data words having the transfer width, and stores the data bus inversion…
DROOP DETECTION AND CONTROL OF DIGITAL FREQUENCY-LOCKED LOOP
Granted: June 22, 2023
Application Number:
20230198528
A apparatus includes a reference signal generator, a droop detection circuit, a digital frequency-locked loop (DFLL), and a DFLL control circuit. The reference signal generator that receives a digital value and produces a pulse-density modulated signal based on the digital value. The droop detection circuit converts the pulse-density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop of the monitored supply…
ELECTRONIC DEVICE INCLUDING AN INTEGRATED CIRCUIT DIE AND A SUPPORT STRUCTURE
Granted: June 22, 2023
Application Number:
20230197623
An electronic device includes a first integrated circuit die, a support structure, and a second integrated circuit die and may include a spacer. The support structure includes a circuit element. The support structure has a thickness of at least 110 microns. The spacer or second integrated circuit die includes a conductor. The spacer or second integrated circuit die is disposed between the first integrated circuit die and the support structure. The conductor is electrically coupled to the…
METHOD AND APPARATUS FOR PERFORMING A SIMULATED WRITE OPERATION
Granted: June 22, 2023
Application Number:
20230197123
A method and apparatus for performing a simulated write in a computer system includes, responsive to a scheduled memory operation determined by a memory controller, sending a simulated write operation to a physical layer circuitry (PHY) to increase circuit power without enabling the output of the PHY until the memory operation begins. Responsive to the memory operation being complete, sending a simulated write operation to the PHY to decrease circuit power.
OVERLAY TREES FOR RAY TRACING
Granted: June 22, 2023
Application Number:
20230196669
Devices and methods for using ray tracing to render similar but different objects in a scene are described which include rendering a second object using an overlay hierarchy tree. The overlay hierarchy tree comprises shared data from a base hierarchy tree comprising data representing a first object in the scene, a second hierarchy tree representing the second object in the scene, difference data representing a difference between the first object and the second object and indication…
COHERENT BLOCK READ FULFILLMENT
Granted: June 22, 2023
Application Number:
20230195662
A coherent memory fabric includes a plurality of coherent master controllers and a coherent slave controller. The plurality of coherent master controllers each include a response data buffer. The coherent slave controller is coupled to the plurality of coherent master controllers. The coherent slave controller, responsive to determining a selected coherent block read command is guaranteed to have only one data response, sends a target request globally ordered message to the selected…
LAST LEVEL CACHE ACCESS DURING NON-CSTATE SELF REFRESH
Granted: June 22, 2023
Application Number:
20230195644
A data processor includes a data fabric, a memory controller, a last level cache, and a traffic monitor. The data fabric is for routing requests between a plurality of requestors and a plurality of responders. The memory controller is for accessing a volatile memory. The last level cache is coupled between the memory controller and the data fabric. The traffic monitor is coupled to the last level cache and operable to monitor traffic between the last level cache and the memory…
Guided Cache Replacement
Granted: June 22, 2023
Application Number:
20230195641
Guided cache replacement is described. In accordance with the described techniques, a request to access a cache is received, and a cache replacement policy which controls loading data into the cache is accessed. The cache replacement policy includes a tree structure having nodes corresponding to cachelines of the cache and a traversal algorithm controlling traversal of the tree structure to select one of the cachelines. Traversal of the tree structure is guided using the traversal…
Cache Associativity Allocation
Granted: June 22, 2023
Application Number:
20230195640
Cache associativity allocation is described. In accordance with the described techniques, a portion of associativity of a cache is allocated to a category of cache requests. The portion of associativity corresponds to a subset of cachelines of the cache. A request is received to access the cache, and a cacheline of the subset of cachelines is allocated to the request based on a category associated with the request. Data corresponding to the request is loaded into the cacheline of the…
PROBE FILTER DIRECTORY MANAGEMENT
Granted: June 22, 2023
Application Number:
20230195632
A data processing system includes a plurality of coherent masters, a plurality of coherent slaves, and a coherent data fabric. The coherent data fabric has upstream ports coupled to the plurality of coherent masters and downstream ports coupled to the plurality of coherent slaves for selectively routing accesses therebetween. The coherent data fabric includes a probe filter and a directory cleaner. The probe filter is associated with at least one of the downstream ports and has a…
Data Routing for Efficient Decompression of Compressed Data Stored in a Cache
Granted: June 22, 2023
Application Number:
20230195625
Data routing for efficient decompressor use is described. In accordance with the described techniques, a cache controller receives requests from multiple requestors for elements of data stored in a compressed format in a cache. The requests include at least a first request from a first requestor and a second request from a second requestor. A decompression routing system identifies a redundant element of data requested by both the first requestor and the second requestor and causes…
SYSTEM AND METHOD TO REDUCE POWER DOWN ENTRY AND EXIT LATENCY
Granted: June 22, 2023
Application Number:
20230195204
A system and method for fast save/restore is disclosed. The system and method include one or more logical units (LUs) residing in independent power domains, one or more digital frequency synthesizers (DFS), each of the one or more DFS associated with one of the one or more LUs, the one or more DFSs configured to lock a system complex frequency and ramp the one or more LUs to system complex frequency, and one or more slave fast save/restore control (FSRC) units, each slave FSRC unit…
FAST DROOP DETECTION CIRCUIT
Granted: June 22, 2023
Application Number:
20230195191
A power supply monitor includes a droop detection circuit which receives a digital signal and converts the digital signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop below a designated value relative to the analog signal, produces a droop detection signal. The droop detection circuit includes a first comparator circuit with a series of inverters including at least a first complimentary-metal-oxide-semiconductor (CMOS)…
METHOD AND SYSTEM FOR INTEGRATING COMPRESSION
Granted: June 15, 2023
Application Number:
20230186523
A method and apparatus for integrating data compression in a computer system includes receiving first data at a first system level. Based upon a number of planes of the first data being less than or equal to a threshold, the data is compressed with a first data compression scheme, and transferred to a second system level for processing. Based upon the number of planes of the first data exceeding the threshold, the first data is transferred uncompressed to the second system level for…
Automatic Key Rolling for Link Encryption
Granted: June 15, 2023
Application Number:
20230188336
Automatic key rolling for link encryption is described. In accordance with the described techniques, data packets are encrypted at a first endpoint of a communication link using a first data encryption key. The encrypted data packets are communicated over the communication link to a second endpoint. A key rolling event that is known by both the first endpoint and the second endpoint is detected at the first endpoint. Responsive to detecting the key rolling event, the first data…
SEMICONDUCTOR CHIP DEVICE
Granted: June 15, 2023
Application Number:
20230187364
An embodiment of a semiconductor chip device can include a molding layer having a first side and a second side, an interconnect chip at least partially encased in the molding layer, the interconnect chip comprising a through substrate via (TSV) that extends through the interconnect chip, an insulating layer positioned on the first side of the molding layer, and a conductive structure that is positioned vertically below the interconnect chip and extends through the insulating layer,…
METHOD AND APPARATUS FOR RECOVERING REGULAR ACCESS PERFORMANCE IN FINE-GRAINED DRAM
Granted: June 15, 2023
Application Number:
20230186976
A fine-grained dynamic random-access memory (DRAM) includes a first memory bank, a second memory bank, and a dual mode I/O circuit. The first memory bank includes a memory array divided into a plurality of grains, each grain including a row buffer and input/output (I/O) circuitry. The dual-mode I/O circuit is coupled to the I/O circuitry of each grain in the first memory bank, and operates in a first mode in which commands having a first data width are routed to and fulfilled…
