EFFICIENT MEMORY POWER CONTROL OPERATIONS
Granted: January 4, 2024
Application Number:
20240004560
A data processor is adapted to couple to a memory. The data processor includes a memory operation array, a power engine, and an initialization circuit. The memory operation array includes a command portion and a data portion. The power engine has an input for receiving power state change request signals and an output for providing memory operations responsive to instructions stored in the command portion. The initialization circuit populates the data portion such that consecutive memory…
SCHEDULING TRAINING OF AN INTER-CHIPLET INTERFACE
Granted: January 4, 2024
Application Number:
20240004815
Systems and methods are disclosed for scheduling a data link training by a controller. The system and method include receiving an indication that a physical layer of a data link is not transferring data and initiating a training process of the physical layer of the data link in response to the indication that the physical layer of the data link is not transferring data. In one aspect, the indication that the physical layer of a data link is not transferring data is an indication that the…
DATA ENCRYPTION SUITABLE FOR USE IN SYSTEMS WITH PROCESSING-IN-MEMORY
Granted: January 4, 2024
Application Number:
20240004801
An encryption circuit includes an iterative block cipher circuit. The iterative block cipher circuit has a counter input for a row index, a key input for receiving a secret key, and an output for providing an encrypted counter value in response to performing a block cipher process using the row index as a counter the secret key. The encryption circuit uses the iterative block cipher circuit during a row operation to a memory.
APPARATUS, SYSTEM, AND METHOD FOR MAKING EFFICIENT PICKS OF MICRO-OPERATIONS FOR EXECUTION
Granted: January 4, 2024
Application Number:
20240004665
A disclosed method for making efficient picks of micro-operations for execution includes selecting a first set of micro-operations that are ready for execution during a certain clock cycle. The method also includes selecting a second set of micro-operations that are ready for execution during the certain clock cycle. The method additionally includes replacing one or more of the complex micro-operations included in the first set of micro-operations with one or more simple micro-operations…
SPLIT REGISTER LIST FOR RENAMING
Granted: January 4, 2024
Application Number:
20240004664
The disclosed system may include a processor configured to detect that a data unit size for an instruction is smaller than a register. The processor may allocate a first portion of the register to the instruction in a manner that leaves a second portion of the register available for allocating to an additional instruction. The processor may also track the register as a split register. Various other methods, systems, and computer-readable media are also disclosed.
ENCODED DATA DEPENDENCY MATRIX FOR POWER EFFICIENCY SCHEDULING
Granted: January 4, 2024
Application Number:
20240004657
The disclosed system may include a processor configured to encode, using an encoding scheme that reduces a number of bits needed to represent one or more instructions from a set of instructions in an instruction buffer represented by a dependency matrix, a dependency indicating that a child instruction represented in the dependency matrix depends on a parent instruction represented in the dependency matrix. The processor may also be configured to store the encoded dependency in the…
ACCELERATING PREDICATED INSTRUCTION EXECUTION IN VECTOR PROCESSORS
Granted: January 4, 2024
Application Number:
20240004656
Methods and systems are disclosed for processing a vector by a vector processor. Techniques disclosed include receiving predicated instructions by a scheduler, each of which is associated with an opcode, a vector of elements, and a predicate. The techniques further include executing the predicated instructions. Executing a predicated instruction includes compressing, based on an index derived from a predicate of the instruction, elements in a vector of the instruction, where the elements…
Intermediate Representation Controller Circuit for Selecting Hardware Compute Units to Process Microcode According to Identified Intermediate Representation Primitives
Granted: January 4, 2024
Application Number:
20240004645
An intermediate representation (IR) controller is described that, for a given intermediate representation (IR) primitive, selects a hardware compute unit of a plurality of hardware compute units. In a non-limiting example, the IR controller receives an input that specifies an IR primitive, a device mask indicating a type of hardware circuitry to be used to process the primitive, and a goal vector specifying a goal in the processing of the primitive. The IR controller also collects data…
DRAM Row Management for Processing in Memory
Granted: January 4, 2024
Application Number:
20240004584
In accordance with described techniques for DRAM row management for processing in memory, a plurality of instructions are obtained for execution by a processing in memory component embedded in a dynamic random access memory. An instruction is identified that last accesses a row of the dynamic random access memory, and a subsequent instruction is identified that first accesses an additional row of the dynamic random access memory. A first command is issued to close the row and a second…
PROTOCOL FOR DATA POISONING
Granted: January 4, 2024
Application Number:
20240004583
A random-access memory (RAM) includes a plurality of memory banks, a memory channel interface circuit, and a metadata processing circuit. The memory channel interface circuit couples to a memory channel adapted for coupling to a memory controller. The metadata processing circuit is connected to the memory channel interface circuit and receiving a poison bit sent over the memory channel associated with a write command and write data for the write command. The RAM, responsive to the poison…
TECHNIQUES FOR REDUCING PROCESSOR POWER CONSUMPTION
Granted: January 4, 2024
Application Number:
20240004453
Methods and systems are disclosed for managing the power consumed by cores of a system on chip (SoC). Techniques disclosed include obtaining application information that is indicative of an application being executed on the cores, detecting a workload associated with the application, and limiting one or more operating frequencies of the cores responsive to the detection of the workload. Techniques disclosed also include profiling the detected workload and limiting the one or more…
REST-OF-CHIP POWER OPTIMIZATION THROUGH DATA FABRIC PERFORMANCE STATE MANAGEMENT
Granted: January 4, 2024
Application Number:
20240004444
Methods and systems are disclosed for managing performance states of a data fabric of a system on chip (SoC). Techniques disclosed include determining a performance state of the data fabric based on data fabric bandwidth utilizations of respective components of the SoC. A metric, characteristic of a workload centric to cores of the SoC, is derived from hardware counters, and, based on the metric, it is determined whether to alter the performance state.
PHASE DETECTION TECHNIQUES FOR HALF-SHIELD PHASE-DETECT SENSORS
Granted: January 4, 2024
Application Number:
20240003748
Techniques for performing phase detect operations are described. The techniques include obtaining first measurements with a set of half-shield phase-detect sensors; obtaining second measurements with a set of non-phase detect sensors that are not configured as phase-detect sensor; and determining a phase difference based on the first measurements and the second measurements.
DEPTH MAP CONSTRUCTION BY CAMERA PHASE DETECTION AND LENS CALIBRATION
Granted: January 4, 2024
Application Number:
20240003680
Techniques for generating a depth map are described. The techniques include obtaining a set of phase difference measurements with a phase detect sensor, and generating a depth map based on the set of phase difference measurements, utilizing a first set of calibration data correlating phase difference measurements with lens defocus data and a second set of calibration data correlating lens positions with object distances.
LIVE PROFILE-DRIVEN CACHE AGING POLICIES
Granted: December 28, 2023
Application Number:
20230418744
A technique for operating a cache is disclosed. The technique includes recording access data for a first set of memory accesses of a first frame; identifying parameters for a second set of memory accesses of a second frame subsequent to the first frame, based on the access data; and applying the parameters to the second set of memory accesses.
NOISE MITIGATION IN SINGLE-ENDED LINKS
Granted: December 28, 2023
Application Number:
20230421203
An integrated circuit includes a first terminal for receiving a data signal, a second terminal for receiving an external reference voltage, a receiver, and a reference voltage generation circuit. The receiver is powered by a power supply voltage with respect to ground and has a first input coupled to the first terminal, a second input for receiving a shared reference voltage, and an output for providing a data input signal. The reference voltage generation circuit is coupled to the…
CHANNEL ROUTING FOR SIMULTANEOUS SWITCHING OUTPUTS
Granted: December 28, 2023
Application Number:
20230420018
A data processor is for accessing a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent, a memory controller, and a data fabric. The at least one memory accessing agent generates generating memory access requests including first memory access requests that access the memory. The memory controller provides memory commands to the memory in response to the first memory access requests. The data fabric routes the…
MEMORY CONTROLLER WITH PSEUDO-CHANNEL SUPPORT
Granted: December 28, 2023
Application Number:
20230418772
A data processor accesses a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent for generating a memory access request, a memory controller for providing a memory command to the memory in response to a normalized request selectively using a first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit, and a data fabric for converting the memory access request into the normalized request…
ALLOCATION CONTROL FOR CACHE
Granted: December 28, 2023
Application Number:
20230418753
A technique for operating a cache is disclosed. The technique includes based on a workload change, identifying a first allocation permissions policy; operating the cache according to the first allocation permissions policy; based on set sampling, identifying a second allocation permissions policy; and operating the cache according to the second allocation permissions policy.
TECHNIQUE TO ENABLE SIMULTANEOUS USE OF ON-DIE SRAM AS CACHE AND MEMORY
Granted: December 28, 2023
Application Number:
20230418745
A technique for operating a cache is disclosed. The technique includes utilizing a first portion of a cache in a directly accessed manner; and utilizing a second portion of the cache as a cache.
