Automated Memory Overclocking
Granted: July 4, 2024
Application Number:
20240220108
Automated memory overclocking is described. In accordance with the described techniques, one or more sets of overclocked memory settings of a memory are automatically selected for performance testing and stability testing of the memory. The one or more sets of the overclocked memory settings are tested for performance of the memory and a performance indication is output for each of the one or more sets of the overclocked memory settings. The one or more sets of the overclocked memory…
FULL DYNAMIC POST-PACKAGE REPAIR
Granted: July 4, 2024
Application Number:
20240220379
A memory controller includes a command queue, an arbiter, and a controller. The controller is responsive to a repair signal for migrating data from a failing region of a memory to a buffer, generating at least one command to perform a post-package repair operation of the failing region, and migrating the data from the buffer to a substitute region of the memory. The controller migrates the data to and from the buffer by providing migration read requests and migration write requests,…
Processing Element-Centric All-to-All Communication
Granted: July 4, 2024
Application Number:
20240220336
In accordance with described techniques for PE-centric all-to-all communication, a distributed computing system includes processing elements, such as graphics processing units, distributed in clusters. An all-to-all communication procedure is performed by the processing elements that are each configured to generate data packets in parallel for all-to-all data communication between the clusters. The all-to-all communication procedure includes a first stage of intra-cluster parallel data…
SYSTEMS AND METHODS FOR SHARING MEMORY ACROSS CLUSTERS OF DIRECTLY CONNECTED NODES
Granted: July 4, 2024
Application Number:
20240220320
An exemplary system comprises a cluster of nodes that are communicatively coupled to one another via at least one direct link and collectively include a plurality of memory devices. The exemplary system also comprises at least one system memory manager communicatively coupled to the cluster of nodes. In one example, the system memory manager is configured to allocate a plurality of sharable memory pools across the memory devices. Various other systems, methods, and computer-readable…
Resource Access Control
Granted: July 4, 2024
Application Number:
20240220265
Resource access control is described. In accordance with the described techniques, a process (e.g., an application process, a system process, etc.) issues an instruction seeking access to a computation resource (e.g., a processor resource, a memory resource, etc.) to perform a computation task. An execution context for the instruction is checked to determine whether the execution context includes a resource indicator indicating permission to access the processor resource. Alternatively…
PIM Search Stop Control
Granted: July 4, 2024
Application Number:
20240220251
In accordance with described techniques for processing-in-memory (PIM) search stop control, a computing system or computing device includes a memory system that includes a stop condition check component, which receives an instruction that includes a programmed check value. The stop condition check component compares the programmed check value to outputs of a PIM component, and the stop condition check component initiates a stop instruction to stop the PIM component from processing…
Permute Instructions for Register-Based Lookups
Granted: July 4, 2024
Application Number:
20240220247
Permute instructions for register-based lookups is described. In accordance with the described techniques, a processor is configured to perform a register-based lookup by retrieving a first result from a first lookup table based on a subset of bits included in an index of a destination register, retrieving a second result from a second lookup table based on the subset of bits included in the index of the destination register, selecting the first result or the second result based on a bit…
Induced Signal Marginality for Random Number Generation
Granted: July 4, 2024
Application Number:
20240220208
Induced signal marginality for random number generation is described. In accordance with the described techniques, a pseudorandom number is transmitted across an interface while the interface is operated with settings configured to cause instability in the interface. A random number is received as an output of the interface. The settings configured to cause instability in the interface include overclocked settings of interface operating parameters.
Scheduling Processing-in-Memory Transactions
Granted: July 4, 2024
Application Number:
20240220160
Scheduling processing-in-memory transactions is described. In accordance with the described techniques, a memory controller receives a transaction header from a host, where the transaction header describes a number of operations to be executed by a processing-in-memory component as part of performing the transaction. The memory controller adds the transaction header to a buffer and sends either an acknowledgement message or a negative acknowledgement message to the host, based on a…
Partial Address Memory Requests
Granted: July 4, 2024
Application Number:
20240220122
Partial address memory requests for data are described. In accordance with the described techniques, an accelerator receives a request for data that does not include address information for a data storage location from which the data is to be retrieved. The accelerator identifies at least one data storage location that includes data produced by the accelerator and retrieves the data from the at least one data storage location. A result is then output by the accelerator that includes the…
Adaptive Scheduling of Memory and Processing-in-Memory Requests
Granted: July 4, 2024
Application Number:
20240220107
Adaptive scheduling of memory requests and processing-in-memory requests is described. In accordance with the described techniques, a memory controller receives a plurality of processing-in-memory requests and a plurality of non-processing-in-memory requests from a host. The memory controller schedules an order of execution for the plurality of processing-in-memory requests and the plurality of non-processing-in-memory requests based at least in part on a processing-in-memory request…
CHIPLET INTERCONNECT POWER STATE MANAGEMENT
Granted: July 4, 2024
Application Number:
20240219988
The disclosed device for power management of chiplet interconnects includes multiple chiplets connected via multiple interconnects. The device also includes a control circuit that detects activity states of the chiplets and manages power states of the interconnects based on the detected activity states. Various other methods, systems, and computer-readable media are also disclosed.
ACCELERATING RELAXED REMOTE ATOMICS ON MULTIPLE WRITER OPERATIONS
Granted: June 27, 2024
Application Number:
20240211134
A memory controller includes an arbiter, a vector arithmetic logic unit (VALU), a read buffer and a write buffer both coupled to the VALU, and an atomic memory operation scheduler. The VALU performs scattered atomic memory operations on arrays of data elements responsive to selected memory access commands. The atomic memory operation scheduler is for scheduling atomic memory operations at the VALU; identifying a plurality of scattered atomic memory operations with commutative and…
LOOKUP TABLE OPTIMIZATION FOR HIGH SPEED TRANSMIT FEED-FORWARD EQUALIZATION LINK
Granted: June 27, 2024
Application Number:
20240214246
A driver circuit includes a feed-forward equalization (FFE) circuit. The FFE circuit receives a plurality of pulse-amplitude modulation (PAM) symbol values to be transmitted at one of multiple PAM levels. The FFE circuit includes a first partial lookup table, one or more additional partial lookup tables, and an adder circuit. The first partial lookup table contains partial finite impulse-response (FIR) values and indexed based on a current PAM symbol value, a precursor PAM symbol value,…
DISTRIBUTED CACHING POLICY FOR LARGE-SCALE DEEP LEARNING TRAINING DATA PRE-PROCESSING
Granted: June 27, 2024
Application Number:
20240211399
A distributed cache network used for machine learning is provided which comprises a network fabric having file systems which store data and a plurality of processing devices, each comprising cache memory and a processor configured to execute a training of a machine learning model and selectively cache portions of the data based on a frequency with which the data is accessed by the processor. Each processing device stores metadata identifying portions of data which are cached in the cache…
Leveraging Processing in Memory Registers as Victim Buffers
Granted: June 27, 2024
Application Number:
20240211393
In accordance with the described techniques for leveraging processing in memory registers as victim buffers, a computing device includes a memory, a processing in memory component having registers for data storage, and a memory controller having a victim address table that includes at least one address of a row of the memory that is stored in the registers. The memory controller receives a request to access the row of the memory and accesses data of the row from the registers based on…
DEVICES, SYSTEMS, AND METHODS FOR INJECTING FABRICATED ERRORS INTO MACHINE CHECK ARCHITECTURES
Granted: June 27, 2024
Application Number:
20240211362
An exemplary system includes and/or represents an agent and a machine check architecture. In one example, the machine check architecture includes and/or represents at least one circuit configured to report errors via at least one reporting register. In this example, the machine check architecture also includes and/or represents at least one error-injection register configured to cause the circuit to inject at least one fabricated error report into the reporting register in response to a…
PERFORMANCE OF BANK REFRESH
Granted: June 27, 2024
Application Number:
20240211173
A memory controller includes an arbiter. The arbiter is configured to elevate a priority of memory access requests that generate row activate commands in response to receiving a same-bank refresh request, and to send a same-bank refresh command in response to receiving the same-bank refresh request.
System Memory Training with Chipset Attached Memory
Granted: June 27, 2024
Application Number:
20240211160
System memory training with chipset attached memory is described. In accordance with the described techniques, a request is received to train a system memory of a device. Responsive to the request, contents of the system memory are transferred to a chipset attached memory. The device is operated using the contents from the chipset attached memory. While the device is being operated using the contents from the chipset attached memory, the system memory is dynamically trained. After the…
Extended Training for Memory
Granted: June 27, 2024
Application Number:
20240211142
Extended training for memory is described. In accordance with the described techniques, a training request to train a memory with extended training is received. The extended training corresponds to a longer amount of time than a default training. The extended training of the memory is performed using a set of target memory settings. In one or more implementations, the extended training is performed during a boot up phase of the computing device.
