MULTI-FREQUENCY VOLTAGE CONVERTER
Granted: August 29, 2024
Application Number:
20240291371
The disclosed voltage regulator includes multiple voltage converter circuits. Each of the voltage converter circuits can be configured to operate at respective switching frequencies to deliver current to an output supply voltage. The voltage regulator can include a control circuit that regulates the output supply voltage using the voltage converter circuits. Various other methods and systems are also disclosed.
UNIFORM CACHE SYSTEM FOR FAST DATA ACCESS
Granted: August 29, 2024
Application Number:
20240289276
A uniform cache for fast data access including a plurality of compute units (CUs) and a plurality of LO caches with an arrangement in a network configuration where each one of CUs is surrounded by a first group of the plurality of LO caches and each of the plurality of LO caches is surrounded by a LO cache group and CU group. One of CUs, upon a request for data, queries the surrounding first group of LO caches to satisfy the request. If the first group of LO caches fails to satisfy the…
COMBINED UPSCALER AND LCEVC ENCODER
Granted: August 22, 2024
Application Number:
20240283955
A disclosed technique includes obtaining input video at a first resolution; upscaling the input video to a second resolution that is higher than the first resolution, using an encoder having a low complexity enhancement video coding encoder that omits at least one component, to generate upscaled video; and encoding the upscaled video using the encoder to generate encoded output video.
VARIABLE RATE BVH TRAVERSAL
Granted: August 22, 2024
Application Number:
20240282044
A technique for performing ray tracing operations is provided. The technique includes, submitting a plurality of intersection test requests to an intersection test unit, wherein the plurality of intersection test requests are submitted prior to receiving results of any of the intersection test requests from the intersection test unit
Multi-Stack Compute Chip and Memory Architecture
Granted: August 15, 2024
Application Number:
20240273040
Multi-stack compute chip and memory architecture is described. In accordance with the described techniques, a package includes a plurality of computing stacks, and each computing stack includes at least one compute chip and a memory. The package also includes one or more interconnects that couple the computing stacks to at least one other computing stack for sharing the memory in a coherent fashion across the plurality of computing stacks.
Automatic Data Layout for Operation Chains
Granted: August 15, 2024
Application Number:
20240272791
Automatic generation of data layout instructions for locating data objects in memory that are involved in a sequence of operations for a computational task is described. In accordance with the described techniques, an interference graph is generated for the sequence of operations, where individual nodes in the interference graph represent data objects involved in the computational task. The interference graph includes edges connecting different pairs of nodes, such that an edge indicates…
DEVICES, SYSTEMS, AND METHODS FOR DETECTING AND MITIGATING SILENT DATA CORRUPTIONS VIA ADAPTIVE VOLTAGE-FREQUENCY SCALING
Granted: August 8, 2024
Application Number:
20240264900
An exemplary computing device includes a plurality of circuits and/or a plurality of in-situ monitors configured to generate outputs that indicate one or more operating conditions of the circuits. The computing device also includes a system management unit configured to detect a potentially faulty voltage-to-frequency ratio implemented by one of the circuits based at least in part on one or more of the outputs. The system management unit is also configured to modify the potentially…
HYBRID BINNING
Granted: August 1, 2024
Application Number:
20240257435
A processing device and a method of tiled rendering of an image for display is provided. The processing device includes memory and a processor. The processor is configured to receive the image comprising one or more three dimensional (3D) objects, divide the image into tiles, execute coarse level tiling for the tiles of the image and execute fine level tiling for the tiles of the image. The processing device also includes same fixed function hardware used to execute the coarse level…
SUPPRESSING CACHE LINE MODIFICATION
Granted: July 18, 2024
Application Number:
20240241827
Disclosed is a system and method for use in a cache for suppressing modification of cache line. The system and method includes a processor and a memory operating cooperatively with a cache controller. The memory includes a coherence directory stored within a cache created to track at least one cache line in the cache via the cache controller. The processor instructs a cache controller to store a first data in a cache line in the cache. The cache controller tags the cache line based on…
VOLTAGE REGULATOR WITH ACTIVE SHUNT
Granted: July 11, 2024
Application Number:
20240235376
The disclosed voltage regulator circuit includes a capacitor bank configured for a first voltage step corresponding to a voltage undershoot, and a shunt circuit configured for a second voltage step exceeding the first voltage step. Various other methods, systems, and computer-readable media are also disclosed.
SHARED CURRENT SENSING UNIT
Granted: July 11, 2024
Application Number:
20240235233
A device is disclosed that includes a battery charge controller having an input removably connected to a power adapter and an output supplying DC current to a battery, a voltage regulator having an input coupled to the output of the battery charge controller and the battery, and a current sensing unit used by the battery charge controller for sensing a charging current to the battery and by the voltage regulator for sensing a discharging current from the battery. Various other methods…
Data Routing for Efficient Decompression of Compressed Data Stored in a Cache
Granted: July 11, 2024
Application Number:
20240232079
Data routing for efficient decompressor use is described. In accordance with the described techniques, a cache controller receives requests from multiple requestors for elements of data stored in a compressed format in a cache. The requests include at least a first request from a first requestor and a second request from a second requestor. A decompression routing system identifies a redundant element of data requested by both the first requestor and the second requestor and causes…
Partial Address Memory Requests
Granted: July 4, 2024
Application Number:
20240220122
Partial address memory requests for data are described. In accordance with the described techniques, an accelerator receives a request for data that does not include address information for a data storage location from which the data is to be retrieved. The accelerator identifies at least one data storage location that includes data produced by the accelerator and retrieves the data from the at least one data storage location. A result is then output by the accelerator that includes the…
TESTING PARITY AND ECC LOGIC USING MBIST
Granted: July 4, 2024
Application Number:
20240221854
A processing device used for MBIST is provided which comprises a data storage structure configured to store data, data protection circuitry configured to add at least one protection bit to corresponding portions of the data written to the data storage structure, data protection checking circuitry configured to identify one or more errors made by the data protection circuitry and an MBIST controller configured to receive the corresponding portions of data written to the data storage…
WRONG WAY READ-BEFORE WRITE SOLUTIONS IN SRAM
Granted: July 4, 2024
Application Number:
20240221805
A static random-access memory (SRAM) circuit includes an SRAM bitcell coupled to a word line, a bit line and a complementary bit line. A precharge circuit is coupled to the bit line and the complementary bit line and includes a precharge input. A first keeper transistor is coupled to the bit line and a second keeper transistor is coupled to the complementary bit line. A write driver circuit includes a select input receiving a select signal, a write data input, and a write data compliment…
TECHNIQUE FOR TESTING RAY FOR INTERSECTION WITH ORIENTED BOUNDING BOXES
Granted: July 4, 2024
Application Number:
20240221284
A technique for performing ray tracing operations is provided. The technique includes determining error bounds for a rotation operation for a ray; selecting a technique for determining whether the ray intersects a bounding box based on the error bounds; and determining whether the ray hits the bounding box based on the selected technique.
PIM Search Stop Control
Granted: July 4, 2024
Application Number:
20240220251
In accordance with described techniques for processing-in-memory (PIM) search stop control, a computing system or computing device includes a memory system that includes a stop condition check component, which receives an instruction that includes a programmed check value. The stop condition check component compares the programmed check value to outputs of a PIM component, and the stop condition check component initiates a stop instruction to stop the PIM component from processing…
Permute Instructions for Register-Based Lookups
Granted: July 4, 2024
Application Number:
20240220247
Permute instructions for register-based lookups is described. In accordance with the described techniques, a processor is configured to perform a register-based lookup by retrieving a first result from a first lookup table based on a subset of bits included in an index of a destination register, retrieving a second result from a second lookup table based on the subset of bits included in the index of the destination register, selecting the first result or the second result based on a bit…
Induced Signal Marginality for Random Number Generation
Granted: July 4, 2024
Application Number:
20240220208
Induced signal marginality for random number generation is described. In accordance with the described techniques, a pseudorandom number is transmitted across an interface while the interface is operated with settings configured to cause instability in the interface. A random number is received as an output of the interface. The settings configured to cause instability in the interface include overclocked settings of interface operating parameters.
Scheduling Processing-in-Memory Transactions
Granted: July 4, 2024
Application Number:
20240220160
Scheduling processing-in-memory transactions is described. In accordance with the described techniques, a memory controller receives a transaction header from a host, where the transaction header describes a number of operations to be executed by a processing-in-memory component as part of performing the transaction. The memory controller adds the transaction header to a buffer and sends either an acknowledgement message or a negative acknowledgement message to the host, based on a…
