AMD Patent Grants

Selecting a resource from a set of resources for performing an operation

Granted: September 19, 2017
Patent Number: 9766936
The described embodiments comprise a selection mechanism that selects a resource from a set of resources in a computing device for performing an operation. In some embodiments, the selection mechanism performs a lookup in a table selected from a set of tables to identify a resource from the set of resources. When the resource is not available for performing the operation and until another resource is selected for performing the operation, the selection mechanism identifies a next…

In-memory interconnect protocol configuration registers

Granted: September 19, 2017
Patent Number: 9767028
Systems, apparatuses, and methods for moving the interconnect protocol configuration registers into the main memory space of a node. The region of memory used for storing the interconnect protocol configuration registers may also be made cacheable to reduce the latency of accesses to the interconnect protocol configuration registers. Interconnect protocol configuration registers which are used during a startup routine may be prefetched into the host's cache to make the startup routine…

Enhancing lifetime of non-volatile cache by reducing intra-block write variation

Granted: September 19, 2017
Patent Number: 9767043
A method, a system and a computer-readable medium for writing to a cache memory are provided. The method comprises maintaining a write count associated with a set, the set containing a memory block associated with a physical block address. A mapping from a logical address to the physical address of the block is also maintained. The method shifts the mapping based on the value of the write count and writes data to the block based on the mapping.

Saving the architectural state of a computing device using sectors

Granted: September 12, 2017
Patent Number: 9760145
A system for saving the architectural state of a processor is described. The system performs a save state operation, which involves, for each sector in a set of sectors of the architectural state, determining whether the architectural state for the sector has already been saved to a memory, and saving the architectural state for the sector to the memory when the architectural state for the sector has not already been saved to the memory. Each sector in the set of sectors comprises a…


Granted: September 12, 2017
Patent Number: 9762248
The arrival time of an asynchronous signal from an asynchronous domain at a synchronizer circuit of a synchronous domain is modified by injecting synchronous domain timing into an additional last stage of the asynchronous logic function generating the asynchronous signal. That reduces the probability of metastability by increasing the probability that the asynchronous signal will arrive at the synchronizer at a time that can guarantee the setup time for the flip-flop(s) of the…

DRAM cache with tags and data jointly stored in physical rows

Granted: September 5, 2017
Patent Number: 9753858
A system and method for efficient cache data access in a large row-based memory of a computing system. A computing system includes a processing unit and an integrated three-dimensional (3D) dynamic random access memory (DRAM). The processing unit uses the 3D DRAM as a cache. Each row of the multiple rows in the memory array banks of the 3D DRAM stores at least multiple cache tags and multiple corresponding cache lines indicated by the multiple cache tags. In response to receiving a…

Multi-protocol header generation system

Granted: September 5, 2017
Patent Number: 9755964
A communication device includes a data source that generates data for transmission over a bus, and a data encoder that receives and encodes outgoing data. An encoder system receives outgoing data from a data source and stores the outgoing data in a first queue. An encoder encodes outgoing data with a header type that is based upon a header type indication from a controller and stores the encoded data that may be a packet or a data word with at least one layered header in a second queue…

Pruning of low power state information for a processor

Granted: August 29, 2017
Patent Number: 9746908
A processor prunes state information based on information provided by software, thereby reducing the amount of state information to be stored prior to the processor entering a low-power state. The software, such as an operating system or application program executing at the processor, indicates one or more registers of the processor as storing data that is no longer useful. When preparing to enter the low-power state, the processor omits the indicated registers from the state information…

Per-block sort for performance enhancement of parallel processors

Granted: August 22, 2017
Patent Number: 9740511
A method of enhancing performance of an application executing in a parallel processor and a system for executing the method are disclosed. A block size for input to the application is determined. Input is partitioned into blocks having the block size. Input within each block is sorted. The application is executed with the sorted input.

Memory management for graphics processing unit workloads

Granted: August 22, 2017
Patent Number: 9740611
A method, a device, and a non-transitory computer readable medium for performing memory management in a graphics processing unit are presented. Hints about the memory usage of an application are provided to a page manager. At least one runtime memory usage pattern of the application is sent to the page manager. Data is swapped into and out of a memory by analyzing the hints and the at least one runtime memory usage pattern.

Technique for translating dependent instructions

Granted: August 15, 2017
Patent Number: 9733941
In response to determining an operation is a dependent operation, a mapper of a processor determines the source registers of the operation from which the dependent operation depends. The mapper translates the dependent operation to a new operation that uses as its source operands at least one of the determined source registers and a source register of the dependent operation. The new operation is independent of other pending operations and therefore can be executed without waiting for…

Methods and apparatus for data cache way prediction based on classification as stack data

Granted: August 15, 2017
Patent Number: 9734059
A method of way prediction for a data cache having a plurality of ways is provided. Responsive to an instruction to access a stack data block, the method accesses identifying information associated with a plurality of most recently accessed ways of a data cache to determine whether the stack data block resides in one of the plurality of most recently accessed ways of the data cache, wherein the identifying information is accessed from a subset of an array of identifying information…

Thin provisioning architecture for high seek-time devices

Granted: August 15, 2017
Patent Number: 9734081
A compute server accomplishes physical address to virtual address translation to optimize physical storage capacity via thin provisioning techniques. The thin provisioning techniques can minimize disk seeks during command functions by utilizing a translation table and free list stored to both one or more physical storage devices as well as to a cache. The cached translation table and free list can be updated directly in response to disk write procedures. A read-only copy of the cached…

Memory page access detection

Granted: August 8, 2017
Patent Number: 9727241
A processor maintains a count of accesses to each memory page. When the accesses to a memory page exceed a threshold amount for that memory page, the processor sets an indicator for the page. Based on the indicators for the memory pages, the processor manages data at one or more levels of the processor's memory hierarchy.

Hybrid tag scheduler to broadcast scheduler entry tags for picked instructions

Granted: August 8, 2017
Patent Number: 9727340
The present invention provides a method and apparatus for scheduling based on tags of different types. Some embodiments of the method include broadcasting a first tag to entries in a queue of a scheduler. The first tag is broadcast in response to a first instruction associated with a first entry in the queue being picked for execution. The first tag includes information identifying the first entry and information indicating a type of the first tag. Some embodiments of the method also…

Method and system of sampling to automatically scale digital power estimates with frequency

Granted: August 8, 2017
Patent Number: 9727435
A method for automatically scaling estimates of digital power consumed by a portion of an integrated circuit (IC) device by the operating frequency of the portion of the IC are described herein. The method may include obtaining an energy value which may correspond to an amount of energy used by the portion of the IC. A cumulative energy value may be generated by repeatedly, at a frequency proportional to the operating frequency of the portion of the IC, obtaining energy values and adding…

Texel shading in texture space

Granted: August 8, 2017
Patent Number: 9728002
A graphics processing unit is configured to map pixels of a first frame of a video stream to texels, select a subset of the texels for shading based on previously cached texels that were shaded for a second frame, and shade the subset of the texels. The graphics processing unit is also configured to cache the shaded subset of the texels with the previously cached texels and determine values for the pixels of the first frame based on the cached texels.

Method and device for noise reduction in multi-frequency clocking environment

Granted: August 1, 2017
Patent Number: 9720486
A device and method of operating a synchronous frequency processing environment served by a common power source and common clock source. The method includes operating the processing environment to have a first power consumption. The method further includes determining a first synchronous frequency processing domain within the processing environment where it is desired to implement a first clock frequency alteration in a clock signal for the first synchronous frequency processing domain.…

Predicting power management state duration on a per-process basis and modifying cache size based on the predicted duration

Granted: August 1, 2017
Patent Number: 9720487
Durations of power management states are predicted on a per-process basis. Some embodiments include storing, in one or more data structures associated with one or more processes, information indicating previous durations of a power management state associated with the process(es). Some embodiments also include predicting a subsequent duration of the power management state for the process(es) using information stored in the data structure(s).

Data layout transformation for workload distribution

Granted: August 1, 2017
Patent Number: 9720708
Techniques are disclosed relating to data transformation for distributing workloads between processors or cores within a processor. In various embodiments, a first processing element receives a set of bytecode. The set of bytecode specifies a set of tasks and a first data structure that specifies data to be operated on during performance of the set of tasks. The first data structure is stored non-contiguously in memory of the computer system. In response to determining to offload the set…