Volume intersection using rotated bounding volumes
Granted: January 7, 2025
Patent Number:
12190447
One or more rotated bounding volumes are generated for one or more nodes of a bounding volume hierarchy (BVH). Volume intersection ray tracing tests are then be performed using the rotated bounding volumes with the aim of reducing the number of calculations required relative to an original, non-rotated bounding volume. Rotated bounding volumes are selected from a plurality of candidate rotations, and selection of one of the candidate rotations are based on surface areas, such as minimum…
Composable neural network kernels
Granted: January 7, 2025
Patent Number:
12190225
A technique for manipulating a generic tensor is provided. The technique includes receiving a first request to perform a first operation on a generic tensor descriptor associated with the generic tensor, responsive to the first request, performing the first operation on the generic tensor descriptor, receiving a second request to perform a second operation on generic tensor raw data associated with the generic tensor, and responsive to the second request, performing the second operation…
Selective workgroup wake-up based on synchronization mechanism identification with high contention scenario
Granted: January 7, 2025
Patent Number:
12190174
A technique for synchronizing workgroups is provided. Multiple workgroups execute a wait instruction that specifies a condition variable and a condition. A workgroup scheduler stops execution of a workgroup that executes a wait instruction and an advanced controller begins monitoring the condition variable. In response to the advanced controller detecting that the condition is met, the workgroup scheduler determines whether there is a high contention scenario, which occurs when the wait…
Suppressing allocation of registers for register renaming
Granted: January 7, 2025
Patent Number:
12190117
Techniques are provided for allocating registers for a processor. The techniques include identifying a first instruction of an instruction dispatch set that meets all register allocation suppression criteria of a first set of register allocation suppression criteria, suppressing register allocation for the first instruction, identifying a second instruction of the instruction dispatch set that does not meet all register allocation suppression criteria of a second set of register…
Tiered memory caching
Granted: January 7, 2025
Patent Number:
12189535
The disclosed computer-implemented method includes locating, from a processor storage, a partial tag corresponding to a memory request for a line stored in a memory having a tiered memory cache and in response to a partial tag hit for the memory request, locating, from a partition of the tiered memory cache indicated by the partial tag, a full tag for the line. The method also includes fetching, in response to a full tag hit, the requested line from the partition of the tiered memory…
Cache blocking for dispatches
Granted: January 7, 2025
Patent Number:
12189534
A processing system divides successive dispatches of work items into portions. The successive dispatches are separated from each other by barriers, each barrier indicating that the work items of the previous dispatch must complete execution before work items of a subsequent dispatch can begin execution. In some embodiments, the processing system interleaves execution of portions of a first dispatch with portions of subsequent dispatches that consume data produced by the first dispatch.…
Suppressing cache line modification
Granted: January 7, 2025
Patent Number:
12189530
Disclosed is a system and method for use in a cache for suppressing modification of cache line. The system and method includes a processor and a memory operating cooperatively with a cache controller. The memory includes a coherence directory stored within a cache created to track at least one cache line in the cache via the cache controller. The processor instructs a cache controller to store a first data in a cache line in the cache. The cache controller tags the cache line based on…
Interrupt cache configuration
Granted: December 31, 2024
Patent Number:
12182611
An apparatus includes an interrupt cache having cache storage configured to store a plurality of interrupts received from an interrupt source, the plurality of interrupts corresponding to a plurality of interrupt events configured for execution by the plurality of interrupt service routines and a cache manager component configured to generate an interrupt message for transmission to the processing unit, the interrupt message generated to include at least one interrupt of the plurality of…
Residual-free palatte mode coding
Granted: December 31, 2024
Patent Number:
12184871
An encoder implements a residual-free palette encoding mode in which a block of pixels is used to derive a palette table having a number of palette colors less than a number of pixel colors in the block of pixels, and to derive a color map representing each pixel of the block with a corresponding index number associated with a palette color that most closely matches the pixel's color. The calculations of residuals representing errors between the predicted palette colors and the actual…
Fan-out packages with warpage resistance
Granted: December 31, 2024
Patent Number:
12183675
Various molded fan-out semiconductor chip devices are disclosed. In one aspect, a semiconductor chip device is provided that includes a first molding layer that has internal conductor structures, a redistribution layer (RDL) structure positioned on the first molding layer and electrically connected to the internal conductor structures, a semiconductor chip positioned on and electrically connected to the RDL structure, and a second molding layer positioned on the RDL structure and at…
Data placement with packet metadata
Granted: December 31, 2024
Patent Number:
12182428
Systems, apparatuses, and methods for determining data placement based on packet metadata are disclosed. A system includes a traffic analyzer that determines data placement across connected devices based on observed values of the metadata fields in actively exchanged packets across a plurality of protocol types. In one implementation, the protocol that is supported by the system is the compute express link (CXL) protocol. The traffic analyzer performs various actions in response to…
Setting durations for which data is stored in a non-volatile memory based on data types
Granted: December 31, 2024
Patent Number:
12182412
An electronic device includes a non-volatile memory and a memory controller. The memory controller selects, from the type-duration table, a duration for which data of a type of data is to be stored in a non-volatile memory. The memory controller writes the data to the non-volatile memory using values of one or more write parameters selected by the memory controller based on the duration. The memory controller sets an expected lifetime value in a record for the data in the expected…
Performance and memory access tracking
Granted: December 31, 2024
Patent Number:
12182396
Techniques for performing memory operations are disclosed herein. The techniques include generating a plurality of performance log entries based on observed operations; generating a plurality of memory access log entries based on the observed operations, wherein each performance log entry of the plurality of performance log entries are associated with one or more memory access log entries of the plurality of memory access log entries, wherein each performance log entry is associated with…
Systems and methods for restoring bus functionality
Granted: December 31, 2024
Patent Number:
12181993
A disclosed method for restoring bus functionality includes detecting, by an automatic bus recovery block, that at least one target device on a bus pulls at least one line of the bus to a low level. The method also includes initiating, by the automatic bus recovery block, a timer to time a duration of the low level of the line. Additionally, the method includes detecting, by the automatic bus recovery block, that the duration of the low level of the line exceeds a predetermined time…
Method and apparatus for fault prediction and management
Granted: December 31, 2024
Patent Number:
12181959
A method and apparatus for predicting and managing a fault in memory includes detecting an error in data. The error is compared to one or more stored errors in a filter, and based upon the comparison, the error is predicted as a transient error or a permanent error for further action.
Systems and methods for enabling debugging
Granted: December 31, 2024
Patent Number:
12181955
A computer-implemented method for enabling debugging can include receiving, at a peripheral device connected through an expansion socket to a base CPU platform, a scan dump instruction from a network computing device connected to the base CPU platform across a network connection and executing, by a System-on-Chip at the peripheral device in response to the scan dump instruction, a debugging procedure. The debugging procedure can include capturing a snapshot of memory of the peripheral…
Method and apparatus for managing power states
Granted: December 31, 2024
Patent Number:
12181944
A method and apparatus for managing power states in a computer system includes, responsive to an event received by a processor, powering up a first circuitry. Responsive to the event not being serviceable by the first circuitry, powering up at least a second circuitry of the computer system to service the event.
Detecting personal-space violations in artificial intelligence based non-player characters
Granted: December 24, 2024
Patent Number:
12172081
Systems, apparatuses, and methods for detecting personal-space violations in artificial intelligence (AI) based non-player characters (NPCs) are disclosed. An AI engine creates a NPC that accompanies and/or interacts with a player controlled by a user playing a video game. During gameplay, measures of context-dependent personal space around the player and/or one or more NPCs are generated. A control circuit monitors the movements of the NPC during gameplay and determines whether the NPC…
Periodic receiver clock data recovery with dynamic data edge
Granted: December 24, 2024
Patent Number:
12174769
Systems, apparatuses, and methods for implementing a periodic receiver clock data recovery scheme with dynamic data edge paths are disclosed. An IQ link calibration scheme performs a non-destructive data and edge path switch to determine an IQ offset without disturbing the data. A data path and an edge path pass through multiple stages of deserializers to widen the data path, with the deserializers clocked by clock divided versions of the original data and edge clocks. To initiate a…
Last level cache access during non-Cstate self refresh
Granted: December 24, 2024
Patent Number:
12174747
A data processor includes a data fabric, a memory controller, a last level cache, and a traffic monitor. The data fabric is for routing requests between a plurality of requestors and a plurality of responders. The memory controller is for accessing a volatile memory. The last level cache is coupled between the memory controller and the data fabric. The traffic monitor is coupled to the last level cache and operable to monitor traffic between the last level cache and the memory…
