Machine learning-based multi-view video conferencing from single view video data
Granted: March 11, 2025
Patent Number:
12250493
Machine learning-based multi-view video conferencing from single view video data, including: identifying, in video data, a plurality of objects; and generating a user interface comprising a plurality of first user interface elements each comprising a portion of the video data corresponding to one or more of the plurality of objects.
Region-based image decompression
Granted: March 11, 2025
Patent Number:
12250379
A method and an apparatus for decoding an image are disclosed. A region of the image is selected and the decoding is selected region and associated metadata is performed. Pixels for a generated for a decoded image based on the decoded selected region and metadata.
Molded chip package with anchor structures
Granted: March 11, 2025
Patent Number:
12249519
Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor…
Wavefront selection and execution
Granted: March 11, 2025
Patent Number:
12248789
Techniques are provided for executing wavefronts. The techniques include at a first time for issuing instructions for execution, performing first identifying, including identifying that sufficient processing resources exist to execute a first set of instructions together within a processing lane; in response to the first identifying, executing the first set of instructions together; at a second time for issuing instructions for execution, performing second identifying, including…
Flexible, scalable graph-processing accelerator
Granted: March 11, 2025
Patent Number:
12248516
An accelerator device includes a first processing unit to access a structure of a graph dataset, and a second processing unit coupled with the first processing unit to perform computations based on data values in the graph dataset.
Apparatus and methods for managing outstanding transactions between one or more requesting units and a target unit
Granted: March 11, 2025
Patent Number:
12248423
An apparatus includes logic circuitry that selects a retag transaction identifier for an original transaction identifier of an incoming transaction request, based on a plurality of sub-groups of retag tracking data. Each sub-group of retag tracking data is associated with a corresponding sub-group of retag transaction identifiers in a group of retag transaction identifiers. The logic circuitry retags the incoming transaction request with the selected retag transaction identifier (ID) by…
Software compilation for networked processing system
Granted: March 4, 2025
Patent Number:
12242828
A compilation technique is provided. The technique includes including a first instruction into a first executable for a first auxiliary processor, wherein the first instruction specifies execution by the first auxiliary processor; and including a second instruction into the first executable, wherein the second instruction targets resources that have affinity with the first auxiliary processor.
Read clock start and stop for synchronous memories
Granted: March 4, 2025
Patent Number:
12243578
A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously, and as a strobe signal that is active only…
Memory calibration system and method
Granted: March 4, 2025
Patent Number:
12243576
A method for performing stutter of dynamic random access memory (DRAM) where a system on a chip (SOC) initiates bursts of requests to the DRAM to fill buffers to allow the DRAM to self-refresh is disclosed. The method includes issuing, by a system management unit (SMU), a ForceZQCal command to the memory controller to initiate the stutter procedure in response to receiving a timeout request, such as an SMU ZQCal timeout request, periodically issuing a power platform threshold (PPT)…
Ranking computing resources
Granted: March 4, 2025
Patent Number:
12242893
A system and method for ranking computing resources in a distributed computing marketplace is disclosed. Ranking may be based on the performance factors that the system predicts will have the greatest impact on the particular application the user plans to run. A performance database stores historical performance data for applications that have been executed on multiple different computer systems. The database is checked to see if the application, or one similar, has already been run on…
Apparatus, system, and method for conducting mission-mode testing on high-speed links
Granted: March 4, 2025
Patent Number:
12242407
An exemplary data fabric device comprises a first traffic moderator configured to receive traffic destined for a specific endpoint accessible via a plurality of data paths and divert the traffic from a first data path included in the data paths to a second data path included in the data paths. The exemplary data fabric device also comprises a first interconnect controller that resides within the second data path and is configured to forward the traffic to the specific endpoint via a…
Compression aware prefetch
Granted: March 4, 2025
Patent Number:
12242384
Methods, devices, and systems for prefetching data. First data is loaded from a first memory location. The first data in cached in a cache memory. Other data is prefetched to the cache memory based on a compression of the first data and a compression of the other data. In some implementations, the compression of the first data and the compression of the other data are determined based on metadata associated with the first data and metadata associated with the other data. In some…
Core activation and deactivation for a multi-core processor
Granted: March 4, 2025
Patent Number:
12242325
Core activation and deactivation for a multi-core processor is described. In accordance with the described techniques, a processor having multiple cores operates using a first core configuration. A request to switch from the first core configuration to a second core configuration is received. Responsive to the request, a switch from the first core configuration to the second core configuration occurs by adjusting a number of active cores of the processor without rebooting.
Device and method for two-stage transitioning between reduced power states
Granted: February 25, 2025
Patent Number:
12235708
Devices and methods for cache prefetching are provided. A device is provided which comprises a quality of service (QOS) component having first assigned registers used to store data to execute a program, a plurality of non-QOS components having second assigned registers used to store data to execute the program and a power management controller, in communication with the QOS component and the non-QOS components. The power management controller is configured to issue fences for the non-QOS…
Circuit board with bridge chiplets
Granted: February 25, 2025
Patent Number:
12238872
Various circuit boards and methods of fabricating and using the same are disclosed. In one aspect, a circuit board is provided that has a substrate with a pocket and a conductor layer. A chiplet is positioned in the pocket. The chiplet has plural bottom side interconnects electrically connected to the conductor layer and plural top side interconnects adapted to interconnect with two or more semiconductor chips.
High-speed die connections using a conductive insert
Granted: February 25, 2025
Patent Number:
12237286
A semiconductor package for high-speed die connections using a conductive insert, the semiconductor package comprising: a die; a plurality of redistribution layers; a conductive insert housed in a perforation through the plurality of redistribution layers; and a conductive bump conductively coupled to an input/output (I/O) connection point of the die via the conductive insert.
Systems and methods for a compressed bitcell read-only memory
Granted: February 25, 2025
Patent Number:
12237026
The disclosed computer-implemented method relating to read-only memory can include (i) asserting a column select signal to select a particular column within a column mux read-only memory, (ii) forwarding, in response to asserting the column select signal, a bit value stored at that particular column to a gate of a transistor that connects a first stage local bitline to a second stage local bitline, and (iii) forwarding an inversion of the bit value to the second stage local bitline…
Bank-level parallelism for processing in memory
Granted: February 25, 2025
Patent Number:
12236134
In accordance with the described techniques for bank-level parallelism for processing in memory, a plurality of commands are received for execution by a processing in memory component embedded in a memory. The memory includes a first bank and a second bank. The plurality of commands include a first stream of commands which cause the processing in memory component to perform operations that access the first bank and a second stream of commands which cause the processing in memory…
Ephemeral data management for cloud computing systems using computational fabric attached memory
Granted: February 25, 2025
Patent Number:
12236109
A cloud computing system includes cloud orchestrator circuitry and fabric manager circuitry. The cloud orchestrator circuitry receives an input application and determines a task graph, a data graph, and a function popularity heap parameter for the input application. The task graph comprises an indication of function interdependency of functions of the input application, the data graph comprises an indication of data interdependency of the functions, and the function popularity heap…
Approach for performing efficient memory operations using near-memory compute elements
Granted: February 25, 2025
Patent Number:
12235756
Near-memory compute elements perform memory operations and temporarily store at least a portion of address information for the memory operations in local storage. A broadcast memory command is then issued to the near-memory compute elements that causes the near-memory compute elements to perform a subsequent memory operation using their respective address information stored in the local storage. This allows a single broadcast memory command to be used to perform memory operations across…
