Super resolution upscaling
Granted: May 6, 2025
Patent Number:
12293485
A first frame of a video stream rendered at a first resolution is obtained. A second frame of the video stream upscaled to a second higher resolution is also obtained. The first plurality of pixels is upscaled to the second resolution. The upsampling generates upsampled color data for the upsampled first plurality of pixels. The upsampled color data is accumulated with a second set of color data associated with a second plurality of pixels defining the second frame to generate final…
Overlay trees for ray tracing
Granted: May 6, 2025
Patent Number:
12293456
A method and a processing device for performing rendering are disclosed. The method comprises generating a base hierarchy tree comprising data representing a first object and generating a second hierarchy tree representing a second object comprising shared data of the base hierarchy tree and the second hierarchy tree and difference data. The method further comprises storing the difference data in the memory without storing the shared data, and generating an overlay hierarchy tree…
Method and apparatus for managing memory
Granted: May 6, 2025
Patent Number:
12293092
A method and apparatus of managing memory includes storing a first memory page at a shared memory location in response to the first memory page including data shared between a first virtual machine and a second virtual machine. A second memory page is stored at a memory location unique to the first virtual machine in response to the second memory page including data unique to the first virtual machine. The first memory page is accessed by the first virtual machine and the second virtual…
Efficient and low power reference voltage mixing
Granted: April 29, 2025
Patent Number:
12288581
A data transmission system includes a first integrated circuit. The first integrated circuit includes a first mixing terminal coupled to a first power supply voltage terminal at a point internal to the first integrated circuit, a first return terminal, a first resistor having a first terminal coupled to the first mixing terminal, and a second terminal for providing a first mixed voltage, and a second resistor having a first terminal coupled to the second terminal of the first resistor,…
Low-latency architecture for full frequency noise reduction in image processing
Granted: April 29, 2025
Patent Number:
12288313
Systems and techniques provide for low-latency, full-frequency noise filtering of images through the use of an image-scaling-based filtering technique, or “multiscale filtering technique”, that can provide filtering for low, medium, and/or high frequencies for one or more components of an image, such that the different resolution scales at each level of the multiscale filtering technique provides a larger receptive field for a denoising process employed at each level than a…
Alternative protocol over physical layer
Granted: April 29, 2025
Patent Number:
12287753
A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a non-PCIe protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol…
Accessing a cache based on an address translation buffer result
Granted: April 29, 2025
Patent Number:
12287739
Address translation is performed to translate a virtual address targeted by a memory request (e.g., a load or memory request for data or an instruction) to a physical address. This translation is performed using an address translation buffer, e.g., a translation lookaside buffer (TLB). One or more actions are taken to reduce data access latencies for memory requests in the event of a TLB miss where the virtual address to physical address translation is not in the TLB. Examples of actions…
Hierarchical depth data generation using primitive fusion
Granted: April 8, 2025
Patent Number:
12272000
Concurrently with performing a visibility pass to generate visibility data for two or more bins of an image, a processing system determines whether a primitive to be rendered covers at least a predetermined threshold percentage of a tile of the image. In response to the primitive coving at least the predetermined threshold percentage of the tile, the processing system stores the depth data of the primitive in a depth buffer for pixel-based rendering. In response to the primitive not…
Cross FET SRAM cell layout
Granted: April 8, 2025
Patent Number:
12274046
A system and method for efficiently creating layout for memory bit cells are described. In various implementations, a memory bit cell uses Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The channels of the vertically stacked transistors use opposite doping polarities. The memory bit cell includes one of a read bit line and a write word line routed in no…
Intelligent allocation of resources in a computing system
Granted: April 8, 2025
Patent Number:
12273277
Systems and methods for allocating computing resources within a distributed computing system are disclosed. Computing resources such as CPUs, GPUs, network cards, and memory are allocated to jobs submitted to the system by a scheduler. System configuration and interconnectivity information is gathered by a mapper and used to create a graph. Resource allocation is optimized based on one or more quality of service (QoS) levels determined for the job. Job performance characterization,…
Off-chip memory shared by multiple processing nodes
Granted: April 8, 2025
Patent Number:
12271627
An apparatus and method for efficiently managing performance among multiple integrated circuits in separate semiconductor chips. In various implementations, a computing system includes at least a first processing node and a second processing node. While processing tasks, the first processing node accesses a first memory and the second processing node accesses a second memory. A first communication channel transfers data between the first and second processing nodes. The first processing…
Memory organization for multi-mode support
Granted: April 8, 2025
Patent Number:
12271597
A memory package includes first, second, third, and fourth channels arranged consecutively in a clockwise direction on the memory package, each of the first, second, third, and fourth channels having access circuitry and memory arrays. In a first mode, the first channel controls access to the memory arrays in the second channel and the fourth channel controls access to the memory arrays in the third channel.
Prioritization of memory traffic for multi-process workloads
Granted: April 8, 2025
Patent Number:
12271588
The disclosed device includes a memory-semantic fabric comprising memory components accessible by multiple processors and a controller for the memory-semantic fabric. The controller receives, from multiple processes, memory requests for a memory-semantic fabric. The controller also identifies, within the processes, a source process for each of the memory requests and prioritizes forwarding the memory requests to the memory-semantic fabric based on the source processes. Various other…
Method and apparatus for managing a cache directory
Granted: April 8, 2025
Patent Number:
12271318
Method and apparatus monitor eviction conflicts among cache directory entries in a cache directory and produce cache directory victim entry information for a memory manager. In some examples, the memory manager reduces future cache directory conflicts by changing a page level physical address assignment for a page of memory based on the produced cache directory victim entry information. In some examples, a scalable data fabric includes hardware control logic that performs the monitoring…
On-demand IP initialization within power states
Granted: April 8, 2025
Patent Number:
12271244
Systems, methods, and devices for integrated circuit power management. A mode of a power management state is entered, from the power management state, in response to an entry condition of the mode. A device that is otherwise powered off in the power management state is powered on in the mode of the power management state. In some implementations, the device includes a communications path between a second device and a third device. In some implementations, the device is in a power domain…
Graphics processing unit (GPU) selection based on a utilized power source
Granted: April 1, 2025
Patent Number:
12265441
Graphics processing unit (GPU) selection based on a utilized power source, including: determining that an apparatus is using a direct current (DC) power source instead of an Alternating Current (AC) power source; and causing, in response to the apparatus using the DC power source, the apparatus to preferentially utilize an integrated graphics processing unit (iGPU) over a discrete graphics processing unit (dGPU) while using the DC power source.
Mixed density interconnect architectures using hybrid fan-out
Granted: April 1, 2025
Patent Number:
12266611
A semiconductor module includes two or more semiconductor dies and an interconnect structure coupled to the two or more semiconductor dies. The interconnect structure implements a plurality of die-to-die connection pathways having a first density and a plurality of fan-out redistribution pathways having a second density that is different from the first density.
Arrangement and thermal management of 3D stacked dies
Granted: April 1, 2025
Patent Number:
12266585
Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.
Approach for processing near-memory processing commands using near-memory register definition data
Granted: April 1, 2025
Patent Number:
12265735
An approach is provided for processing near-memory processing commands, e.g., PIM commands, using PIM register definition data that defines multiple combinations of source and/or destination registers to be used to process PIM commands. A particular combination of source and/or destination registers to be used to process a PIM command is specified by the PIM command or determined by a near-memory processing element processing the PIM command. According to another implementation, the PIM…
Methods for enhanced memory context restore
Granted: April 1, 2025
Patent Number:
12265467
Enhanced methods for memory context restore are described. A device may include a physical layer (PHY) having an interface to support communication of command signals and data with a physical memory. The PHY implements a training mode to train the interface, detect values of a plurality of parameters as part of training the interface, and store the detected values as initial training data. The PHY also implements a retraining mode to use the initial training data as seed data to retrain…
