Method and apparatus for managing memory
Granted: May 6, 2025
Patent Number:
12293092
A method and apparatus of managing memory includes storing a first memory page at a shared memory location in response to the first memory page including data shared between a first virtual machine and a second virtual machine. A second memory page is stored at a memory location unique to the first virtual machine in response to the second memory page including data unique to the first virtual machine. The first memory page is accessed by the first virtual machine and the second virtual…
Overlay trees for ray tracing
Granted: May 6, 2025
Patent Number:
12293456
A method and a processing device for performing rendering are disclosed. The method comprises generating a base hierarchy tree comprising data representing a first object and generating a second hierarchy tree representing a second object comprising shared data of the base hierarchy tree and the second hierarchy tree and difference data. The method further comprises storing the difference data in the memory without storing the shared data, and generating an overlay hierarchy tree…
Super resolution upscaling
Granted: May 6, 2025
Patent Number:
12293485
A first frame of a video stream rendered at a first resolution is obtained. A second frame of the video stream upscaled to a second higher resolution is also obtained. The first plurality of pixels is upscaled to the second resolution. The upsampling generates upsampled color data for the upsampled first plurality of pixels. The upsampled color data is accumulated with a second set of color data associated with a second plurality of pixels defining the second frame to generate final…
Accessing a cache based on an address translation buffer result
Granted: April 29, 2025
Patent Number:
12287739
Address translation is performed to translate a virtual address targeted by a memory request (e.g., a load or memory request for data or an instruction) to a physical address. This translation is performed using an address translation buffer, e.g., a translation lookaside buffer (TLB). One or more actions are taken to reduce data access latencies for memory requests in the event of a TLB miss where the virtual address to physical address translation is not in the TLB. Examples of actions…
Alternative protocol over physical layer
Granted: April 29, 2025
Patent Number:
12287753
A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a non-PCIe protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol…
Low-latency architecture for full frequency noise reduction in image processing
Granted: April 29, 2025
Patent Number:
12288313
Systems and techniques provide for low-latency, full-frequency noise filtering of images through the use of an image-scaling-based filtering technique, or “multiscale filtering technique”, that can provide filtering for low, medium, and/or high frequencies for one or more components of an image, such that the different resolution scales at each level of the multiscale filtering technique provides a larger receptive field for a denoising process employed at each level than a…
Efficient and low power reference voltage mixing
Granted: April 29, 2025
Patent Number:
12288581
A data transmission system includes a first integrated circuit. The first integrated circuit includes a first mixing terminal coupled to a first power supply voltage terminal at a point internal to the first integrated circuit, a first return terminal, a first resistor having a first terminal coupled to the first mixing terminal, and a second terminal for providing a first mixed voltage, and a second resistor having a first terminal coupled to the second terminal of the first resistor,…
Hybrid parallelized tagged geometric (TAGE) branch prediction
Granted: April 22, 2025
Patent Number:
12282776
Hybrid parallelized tagged geometric (TAGE) branch prediction, including: selecting, based on a branch instruction, a first plurality of counts from at least one TAGE table; selecting, based on the branch instruction, a second plurality of counts from at least one non-TAGE branch prediction table; generating, based on the first plurality of counts and a second plurality of counts; and wherein selecting the first plurality of counts and selecting the second plurality of counts are…
Method and apparatus for normalizing an image in an image capturing device
Granted: April 22, 2025
Patent Number:
12284447
A method and apparatus for normalizing an image in an image capturing device includes receiving a processed image by the image device. The processed image is brightness normalized to create a brightness normalized image. The brightness normalized image is provided to an artificial intelligence engine for processing.
Dynamic buffer management in multi-client token flow control routers
Granted: April 22, 2025
Patent Number:
12284116
Systems, apparatuses, and methods for dynamic buffer management in multi-client token flow control routers are disclosed. A system includes at least one or more processing units, a memory, and a communication fabric with a plurality of routers coupled to the processing unit(s) and the memory. A router servicing multiple active clients allocates a first number of tokens to each active client. The first number of tokens is less than a second number of tokens needed to saturate the…
Dynamic page state aware scheduling of read/write burst transactions
Granted: April 22, 2025
Patent Number:
12282439
Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory access requests have not been sent to the memory device in a current mode of a read mode and a write mode, a first cost corresponding to a latency associated with sending remaining requests in either the read queue or the write queue associated with the current mode is determined. If the…
Selective speculative prefetch requests for a last-level cache
Granted: April 22, 2025
Patent Number:
12282428
In response to generating one or more speculative prefetch requests for a last-level cache, a processor determines prefetch analytics for the generated speculative prefetch requests and compares the determined prefetch analytics of the speculative prefetch requests to selection thresholds. In response to a speculative prefetch request meeting or exceeding a selection threshold, the processor selects the speculative prefetch request for issuance to a memory-side cache controller. When one…
Fanout module integrating a photonic integrated circuit
Granted: April 15, 2025
Patent Number:
12276850
A semiconductor package includes a first mold layer at least partially encasing at least one photonic integrated circuit. A redistribution layer structure is fabricated on the first mold layer, the redistribution layer structure including dielectric material and conductive structures. A second mold layer at least partially encasing at least one semiconductor chip is fabricated on the redistribution layer structure. The redistribution layer structure provides electrical pathways between…
Automated data-driven system to optimize overclocking
Granted: April 15, 2025
Patent Number:
12277001
A processing device includes an automated overclocking system and a processor. The automated overclocking system is data-driven and includes an inference engine that executes a machine learning model configured to generate a first output based on a current configuration of the processing device. The first output includes a first set of overclocking parameters. The processor is configured to adjust one or more operating characteristics of at least one component of the processing device…
Default boost mode state for devices
Granted: April 15, 2025
Patent Number:
12277020
One or more components of a computing device are run by default in a boost mode state. The one or more components continue to run in the boost mode state until the boost mode state is no longer sustainable, e.g., due to power consumption of the one or more components or temperature of the one or more components. The one or more components are switched to a reduced power state (e.g., a non-boost mode state) in response to the boost mode state no longer being sustainable. When operating…
Variable bit Morton codes
Granted: April 15, 2025
Patent Number:
12277643
A technique for performing ray tracing operations is provided. The technique includes determining a set of keys and a set of values corresponding to dimensions of a bounding box for a scene; sorting the set of keys and the set of values to generate a sorted set of values; and based on the sorted set of values, generating a Morton code for a triangle of the scene.
Frustum-bounding volume intersection detection using hemispherical projection
Granted: April 15, 2025
Patent Number:
12277644
A frustum bounds a subset of rays projected into a virtual scene to be rendered. The frustum is transformed from a Cartesian coordinate space to a spherical coordinate space using a transform matrix that places a central ray of the frustum as the Z-axis. A projection hemisphere centered around the central ray is defined. The extents of the intersection of the transformed frustum and the surface of the projection hemisphere are bound by a frustum circle. A geometric object in the scene or…
Semiconductor package with annular package lid structure
Granted: April 15, 2025
Patent Number:
12278150
A semiconductor package includes a substrate having opposing first and second surfaces as well as a semiconductor chip component disposed at the second surface and having third and fourth opposing surfaces. A package lid structure is affixed to the second surface of the substrate and the fourth surface of the semiconductor chip component, and has a planar component overlying the semiconductor chip component and having a fifth surface facing the fourth surface and an opposing sixth…
Droop detection and control of digital frequency-locked loop
Granted: April 15, 2025
Patent Number:
12278638
An integrated circuit includes a power supply monitor, a clock generator, and a divider. The power supply monitor is operable to provide a trigger signal in response to a power supply voltage dropping below a threshold voltage. The clock generator is operable to provide a first clock signal having a frequency dependent on a value of a frequency control word, and to change the frequency of the first clock signal over time using a native slope in response to a change in the frequency…
Method and apparatus for managing a cache directory
Granted: April 8, 2025
Patent Number:
12271318
Method and apparatus monitor eviction conflicts among cache directory entries in a cache directory and produce cache directory victim entry information for a memory manager. In some examples, the memory manager reduces future cache directory conflicts by changing a page level physical address assignment for a page of memory based on the produced cache directory victim entry information. In some examples, a scalable data fabric includes hardware control logic that performs the monitoring…
