Processing system with selective priority-based two-level binning
Granted: April 1, 2025
Patent Number:
12266030
Systems and methods related to priority-based and performance-based selection of a render mode, such as a two-level binning mode, in which to execute workloads with a graphics processing unit (GPU) of a system are provided. A user mode driver (UMD) or kernel mode driver (KMD) executed at a central processing unit (CPU) configures low and medium priority workloads to be executed in a two-level binning mode and selects a binning mode for high priority workloads based on whether performance…
Spatial test of bounding volumes for rasterization
Granted: March 25, 2025
Patent Number:
12260494
In response to receiving a scene description, a processing system generates a set of planes in the scene and a bounding volume representing a partition of the scene. Using the set of planes in the scene, a compute unit of an accelerated processing unit performs a spatial test on the bounding volume to determine whether the bounding volume intersects one or more planes of the set of planes in the scene. Based on the spatial test, the compute unit generates intersection data indicating…
System and method for providing system level sleep state power savings
Granted: March 25, 2025
Patent Number:
12260225
A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of…
Guest operating system buffer and log accesses by an input-output memory management unit
Granted: March 25, 2025
Patent Number:
12260120
An electronic device includes a processor that executes a guest operating system; a memory having a guest portion that is reserved for storing data and information to be accessed by the guest operating system; and an input-output memory management unit (IOMMU). The IOMMU writes, in the guest portion, information into guest buffers and/or logs used for communicating information from the IOMMU to the guest operating system. The IOMMU also reads, from the guest portion, information in guest…
Integrated circuit performance adaptation using workload predictions
Granted: March 25, 2025
Patent Number:
12259767
Performance adaptation for an integrated circuit includes receiving, by a workload prediction system of a hardware processor, telemetry data for one or more systems of the hardware processor. A workload prediction is determined by processing the telemetry data through a workload prediction model executed by a workload prediction controller of the workload prediction system. A profile is selected, from a plurality of profiles, that matches the workload prediction. The selected profile…
Sparse matrix operations using processing-in-memory
Granted: March 18, 2025
Patent Number:
12254195
Sparse matrix operations using processing-in-memory is described. In accordance with the described techniques, a processing-in-memory component of a memory module receives a request for a vector element stored at a first location in memory of the memory module. The processing-in-memory component identifies an index value for a non-zero element in a sparse matrix using a representation of the sparse matrix stored at a second location in the memory. The processing-in-memory component then…
Reconfigurable virtual graphics and compute processor pipeline
Granted: March 18, 2025
Patent Number:
12254527
A graphics processing unit (GPU) includes a plurality of programmable processing cores configured to process graphics primitives and corresponding data and a plurality of fixed-function hardware units. The plurality of processing cores and the plurality of fixed-function hardware units are configured to implement a configurable number of virtual pipelines to concurrently process different command flows. Each virtual pipeline includes a configurable number of fragments and an operational…
Control flow invariant resource identification
Granted: March 18, 2025
Patent Number:
12254353
In order to efficiently process graphics data, operations are performed including allocating a first set of resource slots for a first execution instance of a pipeline shader program; correlating the first set of resource slots with graphics pipeline passes; and on a second execution instance of the pipeline shader program, assigning resource slots, from the first set of resource slots, to the graphics pipeline passes, based on the correlating.
Dynamic multi-bank memory command coalescing
Granted: March 18, 2025
Patent Number:
12254217
Systems, apparatuses, and methods for dynamically coalescing multi-bank memory commands to improve command throughput are disclosed. A system includes a processor coupled to a memory via a memory controller. The memory also includes processing-in-memory (PIM) elements which are able to perform computations within the memory. The processor generates memory requests targeting the memory which are sent to the memory controller. The memory controller stores commands received from the…
System and method to reduce power consumption when conveying data to a device
Granted: March 18, 2025
Patent Number:
12254196
Systems, apparatuses, and methods for moving data from a memory in a computing system to an I/O device. A system includes a processor, memory, I/O controller, and power management circuitry. An application stores data in the memory that is to be ultimately conveyed to an I/O device. The I/O controller is configured to convey the data to an I/O device according to a service interval. The I/O controller is configured to fetch a first data item from the memory stored by the application, and…
Method and apparatus for generating artificial intelligence resistant verification images
Granted: March 18, 2025
Patent Number:
12254077
An apparatus includes one or more processors that are configured to determine a pixel-by-pixel bounds for a perturbed image, generate an adversarial example using an adversarial example generation technique, and modify the adversarial example to generate the perturbed image based on the pixel-by-pixel bounds. When an initial perturbed image does not reside within the pixel-by-pixel bounds, the one or more processors adjust the initial perturbed image to generate the perturbed image by a…
Staging memory access requests
Granted: March 18, 2025
Patent Number:
12253961
Staging memory access requests includes receiving a memory access request directed to Dynamic Random Access Memory; storing the memory access request in a staging buffer; and moving the memory access request from the staging buffer to a command queue.
Lid carveouts for processor connection and alignment
Granted: March 18, 2025
Patent Number:
12253892
Package lids with carveouts configured for processor connection and alignment are described. Lid carveouts are configured to align and mechanically secure a cooling device to the package lid by receiving protrusions of the cooling device. Because the lid carveouts ensure precise alignment and orientation of a cooling device relative to a package lid, the lid design enables targeted cooling of discrete portions of the lid. Lid carveouts are further configured to expose one or more…
Machine learning-based multi-view video conferencing from single view video data
Granted: March 11, 2025
Patent Number:
12250493
Machine learning-based multi-view video conferencing from single view video data, including: identifying, in video data, a plurality of objects; and generating a user interface comprising a plurality of first user interface elements each comprising a portion of the video data corresponding to one or more of the plurality of objects.
Region-based image decompression
Granted: March 11, 2025
Patent Number:
12250379
A method and an apparatus for decoding an image are disclosed. A region of the image is selected and the decoding is selected region and associated metadata is performed. Pixels for a generated for a decoded image based on the decoded selected region and metadata.
Molded chip package with anchor structures
Granted: March 11, 2025
Patent Number:
12249519
Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor…
Wavefront selection and execution
Granted: March 11, 2025
Patent Number:
12248789
Techniques are provided for executing wavefronts. The techniques include at a first time for issuing instructions for execution, performing first identifying, including identifying that sufficient processing resources exist to execute a first set of instructions together within a processing lane; in response to the first identifying, executing the first set of instructions together; at a second time for issuing instructions for execution, performing second identifying, including…
Flexible, scalable graph-processing accelerator
Granted: March 11, 2025
Patent Number:
12248516
An accelerator device includes a first processing unit to access a structure of a graph dataset, and a second processing unit coupled with the first processing unit to perform computations based on data values in the graph dataset.
Apparatus and methods for managing outstanding transactions between one or more requesting units and a target unit
Granted: March 11, 2025
Patent Number:
12248423
An apparatus includes logic circuitry that selects a retag transaction identifier for an original transaction identifier of an incoming transaction request, based on a plurality of sub-groups of retag tracking data. Each sub-group of retag tracking data is associated with a corresponding sub-group of retag transaction identifiers in a group of retag transaction identifiers. The logic circuitry retags the incoming transaction request with the selected retag transaction identifier (ID) by…
Read clock start and stop for synchronous memories
Granted: March 4, 2025
Patent Number:
12243578
A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously, and as a strobe signal that is active only…
