Approach for managing near-memory processing commands and non-near-memory processing commands in a memory controller
Granted: August 20, 2024
Patent Number:
12066950
An approach is provided for managing PIM commands and non-PIM commands at a memory controller. A memory controller enqueues PIM commands and non-PIM commands and selects the next command to process based upon various selection criteria. The memory controller maintains and uses a page table to properly configure memory elements, such as banks in a memory module, for the next memory command, whether a PIM command or a non-PIM command. The page table tracks the status of memory elements as…
Color channel correlation detection
Granted: August 20, 2024
Patent Number:
12067749
Systems, apparatuses, and methods for performing color channel correlation detection are disclosed. A compression engine performs a color channel transform on an original set of pixel data to generate a channel transformed set of pixel data. An analysis unit determines whether to compress the channel transformed set of pixel data or the original set of pixel data based on performing a comparison of the two sets of pixel data. In one scenario, the channel transformed set of pixel data is…
Per-pixel variable rate shading controls using stencil data
Granted: August 20, 2024
Patent Number:
12067649
A disclosed technique includes determining a plurality of per-pixel variable rate shading rates for a plurality of fragments; determining a coarse variable shading rate for a coarse variable rate shading area based on the plurality of per-pixel variable rate shading rates; and shading one or more fragments based on the plurality of fragments and based on the coarse variable shading rate.
Memory latency-aware GPU architecture
Granted: August 20, 2024
Patent Number:
12067642
One or more processing units, such as a graphics processing unit (GPU), execute an application. A resource manager selectively allocates a first memory portion or a second memory portion to the processing units based on memory access characteristics. The first memory portion has a first latency that is lower that a second latency of the second memory portion. In some cases, the memory access characteristics indicate a latency sensitivity. In some cases, hints included in corresponding…
Dynamically reconfigurable register file
Granted: August 20, 2024
Patent Number:
12067640
Techniques for managing register allocation are provided. The techniques include detecting a first request to allocate first registers for a first wavefront; first determining, based on allocation information, that allocating the first registers to the first wavefront would result in a condition in which a deadlock is possible; in response to the first determining, refraining from allocating the first registers to the first wavefront; detecting a second request to allocate second…
Cost management in distributed computing teams
Granted: August 20, 2024
Patent Number:
12067557
A method for managing operational costs associated with distributed computing. The method includes: creating, via a graphical user interface (GUI), a distributed computing team; linking a digital team wallet to the distributed computing team, wherein the digital team wallet is linked to a currency account; adding a member to the distributed computing team; allowing the member to purchase compute resource access from a plurality of compute resource providers using the digital team wallet;…
Stream processor with low power parallel matrix multiply pipeline
Granted: August 20, 2024
Patent Number:
12067401
Systems, apparatuses, and methods for implementing a low power parallel matrix multiply pipeline are disclosed. In one embodiment, a system includes at least first and second vector register files coupled to a matrix multiply pipeline. The matrix multiply pipeline comprises a plurality of dot product units. The dot product units are configured to calculate dot or outer products for first and second sets of operands retrieved from the first vector register file. The results of the dot or…
Flexible memory system
Granted: August 20, 2024
Patent Number:
12067237
A technique for operating a memory system is disclosed. The technique includes performing a first request, by a first memory client, to access data at a first memory address, wherein the first memory address refers to data in a first memory section that is coupled to the first memory client via a direct memory connection; servicing the first request via the direct memory connection; performing a second request, by the first client, to access data at a second memory address, wherein the…
Encoding of symbols for a computer interconnect based on frequency of symbol values
Granted: August 20, 2024
Patent Number:
12066965
Data are serially communicated over an interconnect between an encoder and a decoder. The encoder includes a first training unit to count a frequency of symbol values in symbol blocks of a set of N number of symbol blocks in an epoch. A circular shift unit of the encoder stores a set of most-recently-used (MRU) amplitude values. An XOR unit is coupled to the first training unit and the first circular shift unit as inputs and to the interconnect as output. A transmitter is coupled to the…
System direct memory access engine offload
Granted: August 20, 2024
Patent Number:
12066960
Systems, devices, and methods for direct memory access. A system direct memory access (SDMA) device disposed on a processor die sends a message which includes physical addresses of a source buffer and a destination buffer, and a size of a data transfer, to a data fabric device. The data fabric device sends an instruction which includes the physical addresses of the source and destination buffer, and the size of the data transfer, to first agent devices. Each of the first agent devices…
Dynamic banking and bit separation in memories
Granted: August 20, 2024
Patent Number:
12066948
Memories that are configurable to operate in either a banked mode or a bit-separated mode. The memories include a plurality of memory banks; multiplexing circuitry; input circuitry; and output circuitry. The input circuitry inputs at least a portion of a memory address and configuration information to the multiplexing circuitry. The multiplexing circuitry generates read data by combining a selected subset of data corresponding to the address from each of the plurality of memory banks,…
Zero value memory compression
Granted: August 20, 2024
Patent Number:
12066944
A coherency management device receives requests to read data from or write data to an address in a main memory. On a write, if the data includes zero data, an entry corresponding to the memory address is created in a cache directory if it does not already exist, is set to an invalid state, and indicates that the data includes zero data. The zero data is not written to main memory or a cache. On a read, the cache directory is checked for an entry corresponding to the memory address. If…
Data reuse cache
Granted: August 20, 2024
Patent Number:
12066940
Data reuse cache techniques are described. In one example, a load instruction is generated by an execution unit of a processor unit. In response to the load instruction, data is loaded by a load-store unit for processing by the execution unit and is also stored to a data reuse cache communicatively coupled between the load-store unit and the execution unit. Upon receipt of a subsequent load instruction for the data from the execution unit, the data is loaded from the data reuse cache for…
Error-tolerant memory system for machine learning systems
Granted: August 20, 2024
Patent Number:
12066890
A memory system uses error detection codes to detect when errors have occurred in a region of memory. A count of the number of errors is kept and a notification is output in response to the number of errors satisfying a threshold value. The notification is an indication to a host (e.g., a program accessing or managing a machine learning system) that the threshold number of errors have been detected in the region of memory. As long as the number of errors that have been detected in the…
Systems and method for generating Morton code
Granted: August 13, 2024
Patent Number:
12062214
Methods and systems are disclosed for encoding a Morton code. Techniques disclosed comprise receiving location vectors associated with primitives, where the primitives are graphical elements spatially located within a three-dimensional scene. Techniques further comprise determining a code pattern comprising a prefix pattern and a base pattern, and, then, coding each of the location vectors according to the code pattern.
Load multiple primitives per thread in a graphics pipeline
Granted: August 13, 2024
Patent Number:
12062126
Systems, apparatuses, and methods for loading multiple primitives per thread in a graphics pipeline are disclosed. A system includes a graphics pipeline frontend with a geometry engine, shader processor input (SPI), and a plurality of compute units. The geometry engine generates primitives which are accumulated by the SPI into primitive groups. While accumulating primitives, the SPI tracks the number of vertices and primitives per group. The SPI determines wavefront boundaries based on…
Transition into and out of a partially-off power state
Granted: August 13, 2024
Patent Number:
12061510
The computer system responds to a first trigger event to enter a partial off state in which a boot cycle is required to return to a working state. A device plugged into a serial bus port can be charged in the partial off state. A configuration register or runtime environment controls whether the computer system enters the partial off state in response to a trigger event. The computer system stays in the partial off state until another trigger event returns the computer system to the…
Circuit to compensate for temperature impedance drift of conductive component
Granted: August 13, 2024
Patent Number:
12061124
A current control module is employed to protect a conductive feature of a printed circuit board (PCB) from an overcurrent event by comparing a reference voltage output from a compensation circuit connected to a reference power supply to a voltage output from a conductive feature connected to a power supply which is different from the reference power supply. The reference output voltage is representative of an anticipated voltage output from the conductive feature. The current control…
Fast droop detection circuit
Granted: August 6, 2024
Patent Number:
12055991
A power supply monitor includes a droop detection circuit which receives a digital signal and converts the digital signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop below a designated value relative to the analog signal, produces a droop detection signal. The droop detection circuit includes a first comparator circuit with a series of inverters including at least a first complimentary-metal-oxide-semiconductor (CMOS)…
Memory control for data processing pipeline optimization
Granted: August 6, 2024
Patent Number:
12056352
Generating optimization instructions for data processing pipelines is described. A pipeline optimization system computes resource usage information that describes memory and compute usage metrics during execution of each stage of the data processing pipeline. The system additionally generates data storage information that describes how data output by each pipeline stage is utilized by other stages of the pipeline. The pipeline optimization system then generates the optimization…
