Systems and methods for continuous wordline monitoring
Granted: June 11, 2024
Patent Number:
12009047
The disclosed computing device includes a cache memory and at least one processor coupled to the cache memory. The at least one processor is configured to copy data written to one or more nonredundant wordlines of the cache memory to one or more redundant wordlines of the cache memory. The at least one processor is additionally configured to detect a mismatch between data read from the one or more nonredundant wordlines and data stored in the one or more redundant wordlines. The at least…
Weak precharge before write dual-rail SRAM write optimization
Granted: June 11, 2024
Patent Number:
12009025
A method for accessing a memory cell includes enabling precharging of a bit line of the memory cell before a next access of the memory cell. The method includes disabling the precharging after a first interval if the next access is a write. The method includes disabling the precharging after a second interval if the next access is a read. The first interval is shorter than the second interval.
Automatic central processing unit (CPU) usage optimization
Granted: June 11, 2024
Patent Number:
12008401
Automatic central processing unit (CPU) usage optimization includes: monitoring performance activity of a workload comprising a plurality of threads; and modifying a resource allocation of a plurality of cores for the plurality of threads based on the performance activity.
Mechanism for reducing coherence directory controller overhead for near-memory compute elements
Granted: June 11, 2024
Patent Number:
12008378
A parallel processing (PP) level coherence directory, also referred to as a Processing In-Memory Probe Filter (PimPF), is added to a coherence directory controller. When the coherence directory controller receives a broadcast PIM command from a host, or a PIM command that is directed to multiple memory banks in parallel, the PimPF accelerates processing of the PIM command by maintaining a directory for cache coherence that is separate from existing system level directories in the…
Pattern-based cache block compression
Granted: June 4, 2024
Patent Number:
12001237
Systems, methods, and devices for performing pattern-based cache block compression and decompression. An uncompressed cache block is input to the compressor. Byte values are identified within the uncompressed cache block. A cache block pattern is searched for in a set of cache block patterns based on the byte values. A compressed cache block is output based on the byte values and the cache block pattern. A compressed cache block is input to the decompressor. A cache block pattern is…
Read clock toggle at configurable PAM levels
Granted: June 4, 2024
Patent Number:
12002541
A read clock circuit selectively provides a read clock signal from a memory to a memory controller over a memory bus. A pulse-amplitude modulation (PAM) driver including an input and an output capable of driving at least three levels indicating respective digital values. A digital control circuit is coupled to the PAM driver and operable to cause the PAM driver to provide a preamble signal before the read clock signal, the preamble signal including an initial toggling state in which the…
Content feedback based on region of view
Granted: June 4, 2024
Patent Number:
12002128
Content feedback based on region of view, including: determining, for a user of a recipient device receiving content from a presenting device, a region of view of the content associated with the user; generating, based on the region of view, a visual overlay; and displaying, by the presenting device, the visual overlay applied to the content.
Multi-node memory address space for PCIe devices
Granted: June 4, 2024
Patent Number:
12001370
A device in an interconnect network is provided. The device comprises an end point processor comprising end point memory and an interconnect network link in communication with an interconnect network switch. The device is configured to issue, by the end point processor, a request to send data from the end point memory to other end point memory of another end point processor of another device in the interconnect network and provide, to the interconnect network switch, the request using…
Uniform cache system for fast data access
Granted: June 4, 2024
Patent Number:
12001334
A uniform cache for fast data access including a plurality of compute units (CUs) and a plurality of L0 caches with an arrangement in a network configuration where each one of CUs is surrounded by a first group of the plurality of L0 caches and each of the plurality of L0 caches is surrounded by a L0 cache group and CU group. One of CUs, upon a request for data, queries the surrounding first group of L0 caches to satisfy the request. If the first group of L0 caches fails to satisfy the…
Device and method for reducing save-restore latency using address linearization
Granted: June 4, 2024
Patent Number:
12001265
Devices and methods for transitioning between power states of a device are provided. A program is executed using data stored in configuration registers assigned to a component of a device. For a first reduced power state, data of a first portion of the configuration registers is saved to the memory using a first set of linear address space. For a second reduced power state, data of a second portion of the configuration registers is saved to the memory using a second set of linear address…
Compensation for clock frequency modulation
Granted: May 28, 2024
Patent Number:
11996848
The disclosed computer-implemented method includes providing, by a reference clock circuit, a clock signal for a clock-triggered element triggered by the clock signal and modulating, by a frequency modulation circuit, a frequency of the clock signal. The method also includes inserting, by a phase compensation circuit, a phase compensation offset to the modulated clock signal in a manner that compensates for a phase error produced by modulating the frequency of the clock signal. Various…
Adaptable allocation of SRAM based on power
Granted: May 28, 2024
Patent Number:
11996166
A technique for processing computer instructions is provided. The technique includes obtaining information for an instruction state memory entry for an instruction; identifying, for the instruction state memory entry, a slot in an instruction state memory having selectably powered rows and blocks, based on clustering criteria; and placing the instruction state memory entry into the identified slot.
DMA engines configured to perform first portion data transfer commands with a first DMA engine and second portion data transfer commands with second DMA engine
Granted: May 28, 2024
Patent Number:
11995351
A method for hardware management of DMA transfer commands includes accessing, by a first DMA engine, a DMA transfer command and determining a first portion of a data transfer requested by the DMA transfer command. Transfer of a first portion of the data transfer by the first DMA engine is initiated based at least in part on the DMA transfer command. Similarly, a second portion of the data transfer by a second DMA engine is initiated based at least in part on the DMA transfer command.…
Sparse matrix-vector multiplication
Granted: May 28, 2024
Patent Number:
11995149
A processing system includes a first set and a second set of general-purpose registers (GPRs) and memory access circuitry that fetches nonzero values of a sparse matrix into consecutive slots in the first set. The memory access circuitry also fetches values of an expanded matrix into consecutive slots in the second set of GPRs. The expanded matrix is formed based on values of a vector and locations of the nonzero values in the sparse matrix. The processing system also includes a set of…
Memory controller with hybrid DRAM/persistent memory channel arbitration
Granted: May 28, 2024
Patent Number:
11995008
A memory controller includes a command queue having an input for receiving memory access commands for a memory channel, and a number of entries for holding a predetermined number of memory access commands, and an arbiter that selects memory commands from the command queue for dispatch to one of a persistent memory and a DRAM memory coupled to the memory channel. The arbiter includes a first-tier sub-arbiter circuit coupled to the command queue for selecting candidate commands from among…
Systems and methods for generating remedy recommendations for power and performance issues within semiconductor software and hardware
Granted: May 28, 2024
Patent Number:
11994939
The disclosed computer-implemented method for generating remedy recommendations for power and performance issues within semiconductor software and hardware. For example, the disclosed systems and methods can apply a rule-based model to telemetry data to generate rule-based root-cause outputs as well as telemetry-based unknown outputs. The disclosed systems and methods can further apply a root-cause machine learning model to the telemetry-based unknown outputs to analyze deep and complex…
Multi-chiplet clock delay compensation
Granted: May 21, 2024
Patent Number:
11989050
Methods and systems are disclosed for clock delay compensation in a multiple chiplet system. Techniques disclosed include distributing, by a clock generator, a clock signal across distribution trees of respective chiplets; measuring phases, by phase detectors, where each phase measurement is associated with a chiplet of the chiplets and is indicative of a propagation speed of the clock signal through the distribution tree of the chiplet. Then, for each chiplet, techniques are further…
Swizzle mode detection
Granted: May 21, 2024
Patent Number:
11989918
Systems, apparatuses, and methods for converting pixel data to a custom swizzle mode are disclosed. A graphics engine receives data in a pre-defined swizzle mode. The graphics engine determines a custom swizzle mode for the data that has directionality aligned to the data itself to further optimize deltas that are used for compressing the data. The graphics engine groups incoming data into group of two neighboring pixels in both the horizontal and vertical directions. The graphics engine…
Dynamically configurable overprovisioned microprocessor
Granted: May 21, 2024
Patent Number:
11989591
A dynamically configurable overprovisioned microprocessor optimally supports a variety of different compute application workloads and with the capability to tradeoff among compute performance, energy consumption, and clock frequency on a per-compute application basis, using general-purpose microprocessor designs. In some embodiments, the overprovisioned microprocessor comprises a physical compute resource and a dynamic configuration logic configured to: detect an activation-warranting…
Centralized interrupt handling for chiplet processing units
Granted: May 21, 2024
Patent Number:
11989144
Systems, apparatuses, and methods for implementing a centralized interrupt controller to aggregate interrupts generated across multiple semiconductor dies are disclosed. A system includes multiple interrupt sources on multiple semiconductor dies. A centralized interrupt controller on one of the semiconductor dies receives and aggregates interrupts from the multiple interrupt sources on the multiple semiconductor dies. This facilitates a single transmission point for forwarding the…
