Adaptive thread group dispatch
Granted: November 21, 2023
Patent Number:
11822956
One or more shader processor inputs (SPIs) provide work items from a thread group for execution on one or more shader engines. A command processor selectively dispatches the work items to the SPIs based on a size of the thread group and a format of cache lines of a cache implemented in the one or more shader engines. The command processor operates in a tile mode in which the command processor schedules the work items in multidimensional blocks that correspond to the format of the cache…
Performing store-to-load forwarding of a return address for a return instruction
Granted: November 21, 2023
Patent Number:
11822923
A load/store unit includes a first queue including a first entry for a store operation and a second queue including a second entry for a load operation that includes a return instruction that redirects a program flow to a location indicated by the return instruction. The load/store unit also includes a processor to determine that the store operation matches the load operation and selectively perform store-to-load forwarding (STLF) of a return address for the return instruction from the…
Low power cache
Granted: November 21, 2023
Patent Number:
11822484
A cache includes an upstream port, a cache memory for storing cache lines each having a line width, and a cache controller. The cache controller is coupled to the upstream port and the cache memory. The upstream port transfers data words having a transfer width less than the line width. In response to a cache line fill, the cache controller selectively determines data bus inversion information for a sequence of data words having the transfer width, and stores the data bus inversion…
History-based selective cache line invalidation requests
Granted: November 21, 2023
Patent Number:
11822479
Techniques for performing cache operations are provided. The techniques include recording an indication that providing exclusive access of a first cache line to a first processor is deemed problematic; detecting speculative execution of a store instruction by the first processor to the first cache line; and in response to the detecting, refusing to provide exclusive access of the first cache line to the first processor, based on the indication.
Metadata tweak for channel encryption differentiation
Granted: November 14, 2023
Patent Number:
11816228
Systems, apparatuses, and methods for implementing a metadata tweak for channel encryption differentiation are disclosed. A memory controller retrieves a device-unique identifier (ID) from a memory device coupled to a given memory channel slot. The memory controller uses the device-unique ID to generate a tweak value used for encrypting data stored in the device. In one scenario, the device-unique ID is embedded in the address bits of the tweak process. In this way, the memory device can…
Low overhead high bandwidth data transfer protocol
Granted: November 14, 2023
Patent Number:
11818238
A processing system includes a controller of a transmitting module for transmitting data to a receiving module across an interconnect compliant with a processor interconnect protocol. The controller indicates the beginning and end of a variable-length data burst using data primitives that are N symbols (bytes) in length, rather than using data primitives that are M symbols in length, as specified by the processor interconnect protocol, where N<M. The controller of the transmitting…
Real-time low latency computer vision/machine learning compute accelerator with smart convolutional neural network scheduler
Granted: November 14, 2023
Patent Number:
11816871
Methods and devices are provided for processing image data on a sub-frame portion basis using layers of a convolutional neural network. The processing device comprises memory and a processor. The processor is configured to receive frames of image data comprising sub-frame portions, schedule a first sub-frame portion of a first frame to be processed by a first layer of the convolutional neural network when the first sub-frame portion is available for processing, process the first…
Overlay trees for ray tracing
Granted: November 14, 2023
Patent Number:
11816792
Devices and methods for using ray tracing to render similar but different objects in a scene are described which include rendering a second object using an overlay hierarchy tree. The overlay hierarchy tree comprises shared data from a base hierarchy tree comprising data representing a first object in the scene, a second hierarchy tree representing the second object in the scene, difference data representing a difference between the first object and the second object and indication…
Spatial hashing for world-space spatiotemporal reservoir re-use for ray tracing
Granted: November 14, 2023
Patent Number:
11816781
A processor shares path tracing data across sampling locations to amortize computations across space and time. The processor maps a group of sampling locations of a frame that are adjacent to each other in world-space to a cell of a hash table. Each cell of the hash table stores a list of reservoirs that are each associated with a ray that intersects the group of sampling locations from world-space. The processor resamples the reservoirs at the hash table by combining and re-using…
VLIW power management
Granted: November 14, 2023
Patent Number:
11816490
VLIW directed Power Management is described. In accordance with described techniques, a program is compiled to generate instructions for execution by a very long instruction word machine. During the compiling, power configurations for the very long instruction word machine to execute the instructions are determined, and fields of the instructions are populated with the power configurations. In one or more implementations, an instruction that includes a power configuration for the very…
Enhanced page information co-processor
Granted: November 14, 2023
Patent Number:
11816037
A processing system includes a primary processor and a co-processor. The primary processor is couplable to a memory subsystem having at least one memory and operating to execute system software employing memory address translations based on one or more page tables stored in the memory subsystem. The co-processor is likewise couplable to the memory subsystem and operates to perform iterations of a page table walk through one or more page tables maintained for the memory subsystem and to…
Error handling for resilient software
Granted: November 14, 2023
Patent Number:
11815986
Error handling for resilient software includes: receiving data indicating a region of resilient memory; detecting an error associated with a region of memory; and preventing raising an exception for the error in response to the region of memory falling within the region of resilient memory by preventing the region of memory as being identified as including the error.
Bond pads for low temperature hybrid bonding
Granted: November 7, 2023
Patent Number:
11810891
Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a…
Fine-grained conditional dispatching
Granted: November 7, 2023
Patent Number:
11809902
Techniques for executing workgroups are provided. The techniques include executing, for a first workgroup of a first kernel dispatch, a workgroup dependency instruction that includes an indication to prioritize execution of a second workgroup of a second kernel dispatch, and in response to the workgroup dependency instruction, dispatching the second workgroup of the second kernel dispatch prior to dispatching a third workgroup of the second kernel dispatch, wherein no workgroup…
Refresh management list for DRAM
Granted: November 7, 2023
Patent Number:
11809743
A memory controller includes a command queue having a first input for receiving memory access requests, and a memory interface queue having an output for coupling to a memory channel adapted for connecting to at least one dynamic random access memory (DRAM) module. A refresh control circuit monitors activate commands to be sent over the memory channel. In response to an activate command meeting a designated condition, the refresh control circuit identifies a candidate aggressor row…
Hardware security hardening for processor devices
Granted: November 7, 2023
Patent Number:
11809558
A method of packet attribute confirmation includes receiving, at a command processor of a parallel processor, a command packet including a received packet attribute, such as a packet size, of the command packet. The command processor compares the received packet attribute of the command packet relative to an expected packet attribute of the command packet. The command processor passes one or more commands to a prefetch parser such that a summed total size of the one or more commands is…
Region based directory scheme to adapt to large cache sizes
Granted: November 7, 2023
Patent Number:
11809322
Systems, apparatuses, and methods for maintaining a region-based cache directory are disclosed. A system includes multiple processing nodes, with each processing node including a cache subsystem. The system also includes a cache directory to help manage cache coherency among the different cache subsystems of the system. In order to reduce the number of entries in the cache directory, the cache directory tracks coherency on a region basis rather than on a cache line basis, wherein a…
Phase shedding based on phase efficiency determined by pulse width modulator switching of voltage regulator field effect transistors
Granted: November 7, 2023
Patent Number:
11809260
A method of operating a multiphase power supply includes identifying a least efficient phase of a plurality of phases in the multiphase power supply based on a comparison of a pulse width for each phase in the plurality of phases, and decreasing an amount of power supplied to a load by the identified least efficient phase.
System and method for coalesced multicast data transfers over memory interfaces
Granted: October 31, 2023
Patent Number:
11803311
Methods and apparatuses to control digital data transfer via a memory channel between a memory module and a processor are disclosed. At least one of the memory module or the processor coalesces a plurality of short data words into multicast coalesced block data comprising a single data block for transfer via the memory channel. Each of the plurality of short data words pertains to one of at least two partitioned memory submodules in the memory module. The multicast coalesced block data…
Multi-level cache coherency protocol for cache line evictions
Granted: October 31, 2023
Patent Number:
11803470
Disclosed are examples of a system and method to communicate cache line eviction data from a CPU subsystem to a home node over a prioritized channel and to release the cache subsystem early to process other transactions.
