Job scheduling using reinforcement learning
Granted: October 31, 2023
Patent Number:
11803999
Systems, methods, and techniques utilize reinforcement learning to efficiently schedule a sequence of jobs for execution by one or more processing threads. A first sequence of execution jobs associated with rendering a target frame of a sequence of frames is received. One or more reward metrics related to rendering the target frame are selected. A modified sequence of execution jobs for rendering the target frame is generated, such as by reordering the first sequence of execution jobs.…
Adaptive quantization for neural networks
Granted: October 31, 2023
Patent Number:
11803734
Methods, devices, systems, and instructions for adaptive quantization in an artificial neural network (ANN) calculate a distribution of ANN information; select a quantization function from a set of quantization functions based on the distribution; apply the quantization function to the ANN information to generate quantized ANN information; load the quantized ANN information into the ANN; and generate an output based on the quantized ANN information. Some examples recalculate the…
Dynamic application of software data caching hints based on cache test regions
Granted: October 31, 2023
Patent Number:
11803484
A processor applies a software hint policy to a portion of a cache based on access metrics for different test regions of the cache, wherein each test region applies a different software hint policy for data associated with cache entries in each region of the cache. One test region applies a software hint policy under which software hints are followed. The other test region applies a software hint policy under which software hints are ignored. One of the software hint policies is selected…
Computer processing devices with dynamic shared cache line copy retention policy selection
Granted: October 31, 2023
Patent Number:
11803473
Systems and techniques for dynamic selection of policy that determines whether copies of shared cache lines in a processor core complex are to be stored and maintained in a level 3 (L3) cache of the processor core complex are based on one or more cache line sharing parameters or based on a counter that tracks L3 cache misses and cache-to-cache (C2C) transfers in the processor core complex, according to various embodiments. Shared cache lines are shared between processor cores or between…
Multi-level cache coherency protocol for cache line evictions
Granted: October 31, 2023
Patent Number:
11803470
Disclosed are examples of a system and method to communicate cache line eviction data from a CPU subsystem to a home node over a prioritized channel and to release the cache subsystem early to process other transactions.
Write hardware training acceleration
Granted: October 31, 2023
Patent Number:
11803437
A memory includes a link training circuit with a pseudo-random bit sequence (PRBS) generator and a burst error detection counter. The burst error detection counter including a comparator, a first input coupled to the data input, a second input coupled to the PRBS generator, and a counter operable to increase an error count value by one responsive to detecting any number of errors greater than zero in a sequence of symbols including a predetermined number of symbols.
Broadcast synchronization for dynamically adaptable arrays
Granted: October 31, 2023
Patent Number:
11803385
An array processor includes processor element arrays (PEAs) distributed in rows and columns. The PEAs are configured to perform operations on parameter values. A first sequencer received a first direct memory access (DMA) instruction that includes a request to read data from at least one address in memory. A texture address (TA) engine requests the data from the memory based on the at least one address and a texture data (TD) engine provides the data to the PEAs. The PEAs provide first…
System and method for coalesced multicast data transfers over memory interfaces
Granted: October 31, 2023
Patent Number:
11803311
Methods and apparatuses to control digital data transfer via a memory channel between a memory module and a processor are disclosed. At least one of the memory module or the processor coalesces a plurality of short data words into multicast coalesced block data comprising a single data block for transfer via the memory channel. Each of the plurality of short data words pertains to one of at least two partitioned memory submodules in the memory module. The multicast coalesced block data…
Error reporting for non-volatile memory modules
Granted: October 24, 2023
Patent Number:
11797369
A memory controller includes a memory channel controller adapted to receive memory access requests and dispatch associated commands addressable in a system memory address space to a non-volatile storage class memory (SCM) module. The non-volatile error reporting circuit identifies error conditions associated with the non-volatile SCM module and maps the error conditions from a first number of possible error conditions associated with the non-volatile SCM module to a second, smaller…
Protection against branch target buffer poisoning by a management layer
Granted: October 24, 2023
Patent Number:
11797665
A processing system includes a branch prediction structure storing information used to predict the outcome of a branch instruction. The processing system also includes a register storing a first identifier of a first process in response to the processing system changing from a first mode that allows the first process to modify the branch prediction structure to a second mode in which the branch prediction structure is not modifiable. The processing system further includes a processor…
Cache management based on reuse distance
Granted: October 24, 2023
Patent Number:
11797455
A cache of a processor includes a cache controller to implement a cache management policy for the insertion and replacement of cache lines of the cache. The cache management policy assigns replacement priority levels to each cache line of at least a subset of cache lines in a region of the cache based on a comparison of a number of accesses to a cache set having a way that stores a cache line since the cache line was last accessed to a reuse distance determined for the region of the…
Chiplet-level performance information for configuring chiplets in a processor
Granted: October 24, 2023
Patent Number:
11797410
A processor includes a controller and plurality of chiplets, each chiplet including a plurality of processor cores. The controller provides chiplet-level performance information for the chiplets that identifies a performance of each chiplet at each of a plurality of performance levels for specified sets of processor cores on that chiplet. The controller receives an identification of one or more selected chiplets from among the plurality of chiplets for which a specified number of…
Hardware-software collaborative address mapping scheme for efficient processing-in-memory systems
Granted: October 24, 2023
Patent Number:
11797201
Approaches are provided for implementing hardware-software collaborative address mapping schemes that enable mapping data elements which are accessed together in the same row of one bank or over the same rows of different banks to achieve higher performance by reducing row conflicts. Using an intra-bank frame striping policy (IBFS), corresponding subsets of data elements are interleaved into a single row of a bank. Using an intra-channel frame striping policy (ICFS), corresponding…
Multi-accelerator compute dispatch
Granted: October 17, 2023
Patent Number:
11790590
Techniques for executing computing work by a plurality of chiplets are provided. The techniques include assigning workgroups of a kernel dispatch packet to the chiplets; by each chiplet, executing the workgroups assigned to that chiplet; for each chiplet, upon completion of all workgroups assigned to that chiplet for the kernel dispatch packet, notifying the other chiplets of such completion; and upon completion of all workgroups of the kernel dispatch packet, notifying a client of such…
Ray-tracing multi-sample anti-aliasing
Granted: October 17, 2023
Patent Number:
11790593
A technique for performing a ray tracing operation for a ray is provided. The method includes performing one or more ray-box intersection tests for the ray against one or more bounding boxes of a bounding volume hierarchy to eliminate one or more nodes of the bounding volume hierarchy from consideration, for one or more triangles of the bounding volume hierarchy that are not eliminated by the one or more ray-box intersection tests, performing one or more ray-triangle intersection tests…
Methods and devices for testing multiple memory configurations
Granted: October 17, 2023
Patent Number:
11791008
Methods, devices, and systems for testing a number of combinations of memory in a computer system. A modular memory device is installed in a memory channel in communication with a processor. The modular memory device includes a number of memory storage devices. The number of memory storage devices include a number of pins. For each of a number of subsets of the number of memory storage devices, a subset of the number of memory storage devices is selected, each pin of a subset of the…
Dynamic computer marketplace system and method
Granted: October 17, 2023
Patent Number:
11790435
Systems, methods and apparatuses are disclosed for implementation and management of a dynamic compute and application marketplace. The dynamic computer marketplace system can coordinate access to one or more other computing resources, including on-premises computing resources, external (or off-premises) computing resources or a combination thereof. In various embodiments, the dynamic computer marketplace system advantageously can be used to facilitate inter-provider migration,…
Padded vectorization with compile time known masks
Granted: October 17, 2023
Patent Number:
11789734
A computing system includes a processing unit and a memory storing instructions that, when executed by the processor, cause the processor to receive program source code in a compiler, identify in the program source code a set of operations for vectorizing, where each operation in the set of operations specifies a set of one or more operands, in response to identifying the set of operations, vectorize the set of operations by, based on the number of operations in the set of operations and…
Arithmetic logic unit register sequencing
Granted: October 17, 2023
Patent Number:
11789732
A graphics processing unit (GPU) sequences provision of operands to a set of operand registers, thereby allowing the GPU to share at least one of the operand registers between processing. The GPU includes a plurality of arithmetic logic units (ALUs) with at least one of the ALUs configured to perform double precision operations. The GPU further includes a set of operand registers configured to store single precision operands. For a plurality of executing threads that request double…
Efficient and low latency memory access scheduling
Granted: October 17, 2023
Patent Number:
11789655
A memory controller includes a command queue that receives and stores decoded memory commands and information related thereto including information indicating a type, a priority, an age, and a region of a memory system for a corresponding decoded memory command, and an arbiter coupled to the command queue and picks selected decoded memory commands among the decoded memory commands from the command queue for dispatch to the memory system by comparing the priority and the age for decoded…
