Gaming super resolution
Granted: January 3, 2023
Patent Number:
11544815
A processing device is provided which includes memory and a processor. The processor is configured to receive an input image having a first resolution, generate linear down-sampled versions of the input image by down-sampling the input image via a linear upscaling network and generate non-linear down-sampled versions of the input image by down-sampling the input image via a non-linear upscaling network. The processor is also configured to convert the down-sampled versions of the input…
Resource-aware compression
Granted: January 3, 2023
Patent Number:
11544196
Systems, apparatuses, and methods for implementing a multi-tiered approach to cache compression are disclosed. A cache includes a cache controller, light compressor, and heavy compressor. The decision on which compressor to use for compressing cache lines is made based on certain resource availability such as cache capacity or memory bandwidth. This allows the cache to opportunistically use complex algorithms for compression while limiting the adverse effects of high decompression…
GPU networking using an integrated command processor
Granted: January 3, 2023
Patent Number:
11544121
Systems, apparatuses, and methods for generating network messages on a parallel processor are disclosed. A system includes at least a parallel processor, a general purpose processor, and a network interface unit. The parallel processor includes at least a plurality of compute units, a command processor, and a cache. A thread within a kernel executing on a compute unit of the parallel processor generates a network message and stores the network message and a corresponding indication in…
Continuation analysis tasks for GPU task scheduling
Granted: January 3, 2023
Patent Number:
11544106
Systems, apparatuses, and methods for implementing continuation analysis tasks (CATs) are disclosed. In one embodiment, a system implements hardware acceleration of CATs to manage the dependencies and scheduling of an application composed of multiple tasks. In one embodiment, a continuation packet is referenced directly by a first task. When the first task completes, the first task enqueues a continuation packet on a first queue. The first task can specify on which queue to place the…
Bit width reconfiguration using a shadow-latch configured register file
Granted: January 3, 2023
Patent Number:
11544065
A processor includes a front-end with an instruction set that operates at a first bit width and a floating point unit coupled to receive the instruction set in the processor that operates at the first bit width. The floating point unit operates at a second bit width and, based upon a bit width assessment of the instruction set provided to the floating point unit, the floating point unit employs a shadow-latch configured floating point register file to perform bit width reconfiguration.…
Low power state selection based on idle duration history
Granted: January 3, 2023
Patent Number:
11543877
An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of…
Adjustable modulation coding scheme to increase video stream robustness
Granted: December 27, 2022
Patent Number:
11539908
Systems, apparatuses, and methods for utilizing different modulation coding schemes (MCSs) for different components of a video stream are disclosed. A system includes a transmitter sending a video stream over a wireless link to a receiver. The transmitter splits the video stream into low, medium, and high quality components, and then the transmitter modulates the different components using different MCS's. For example, the transmitter modulates the low quality component using a lower,…
Compiler-assisted inter-SIMD-group register sharing
Granted: December 27, 2022
Patent Number:
11537397
Systems, apparatuses, and methods for efficiently sharing registers among threads are disclosed. A system includes at least a processor, control logic, and a register file with a plurality of registers. The processor assigns a base set of registers to each thread of a plurality of threads executing on the processor. When a given thread needs more than the base set of registers to execute a given phase of program code, the given thread executes an acquire instruction to acquire exclusive…
Content addressable memory with sub-field minimum and maximum clamping
Granted: December 27, 2022
Patent Number:
11537319
A processing system includes a content addressable memory (CAM) in an input/output path to selectively modify register writes on a per-pipeline basis. The CAM compares an address of a register write to an address field of each entry of the CAM. If a match is found, the CAM modifies the register write data as defined by a function for the matching entry of the CAM. In some embodiments, each entry of the CAM includes a data mask defining subfields of the register write data, wherein each…
Reduced bandwidth tessellation factors
Granted: December 20, 2022
Patent Number:
11532066
A graphics pipeline reduces the number of tessellation factors written to and read from a graphics memory. A hull shader stage of the graphics pipeline detects whether at least a threshold percentage of the tessellation factors for a thread group of patches are the same and, in some embodiments, whether at least the threshold percentage of the tessellation factors for a thread group of patches have a same value that either indicates that the plurality of patches are to be culled or that…
Error recovery for non-volatile memory modules
Granted: December 20, 2022
Patent Number:
11531601
A memory controller includes a command queue, a memory interface queue, at least one storage queue, and a replay control circuit. The command queue has a first input for receiving memory access commands. The memory interface queue receives commands selected from the command queue and couples to a heterogeneous memory channel which is coupled to at least one non-volatile storage class memory (SCM) module. The at least one storage queue stores memory access commands that are placed in the…
Hybrid library latch array
Granted: December 13, 2022
Patent Number:
11527270
A static random access memory (SRAM) includes fast SRAM bit cells and fast multiplexer circuits that are formed in a first row of fast cells in a hybrid standard cell architecture. Slow SRAM bit cells and slow multiplexer circuits are formed in a second row of slow cells. The slow multiplexer circuits provide a column output for the fast SRAM bit cells and the fast multiplexer circuits provide a column output for the slow SRAM bit cells. Thus, one SRAM column has fast bit cells and slow…
Tessellator sub-patch distribution based on group limits
Granted: December 13, 2022
Patent Number:
11527033
A graphics pipeline includes a tessellator stage having a sub-patch distributor and a plurality of tessellators. The sub-patch distributor divides an input patch into a plurality of sub-primitive groups, with the primitive group limit governing the maximum permissible size for a given group of sub-primitives to be assigned to a tessellator. The sub-patch distributor recursively identifies a plurality of regions of the input patch, with the size and number of primitives of each region…
Limited propagation of unnecessary memory updates
Granted: December 13, 2022
Patent Number:
11526449
A processing system limits the propagation of unnecessary memory updates by bypassing writing back dirty cache lines to other levels of a memory hierarchy in response to receiving an indication from software executing at a processor of the processing system that the value of the dirty cache line is dead (i.e., will not be read again or will not be read until after it has been overwritten). In response to receiving an indication from software that data is dead, a cache controller prevents…
Adaptive page close prediction
Granted: December 13, 2022
Patent Number:
11526278
Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. In various embodiments, a computing system includes one or more computing resources and a memory controller coupled to a memory device. The memory controller determines a memory access request targets a given bank of multiple banks. An access history is updated for the given bank based on whether the memory access request hits on an open page within the given bank and a page…
Residency map descriptors
Granted: December 6, 2022
Patent Number:
11521342
A processor receives a request to access one or more levels of a partially resident texture (PRT) resource. The levels represent a texture at different levels of detail (LOD) and the request includes normalized coordinates indicating a location in the texture. The processor accesses a texture descriptor that includes dimensions of a first level of the levels and one or more offsets between a reference level and one or more second levels that are associated with one or more residency maps…
Ambient occlusion using bounding volume hierarchy bounding box tests
Granted: December 6, 2022
Patent Number:
11521308
A technique for performing a ray intersection test, the method comprising: receiving a request for an early termination ray intersection test for a ray; testing the ray against one or more early termination box nodes and one or more normal box nodes of a bounding volume hierarchy; and based on the test of the ray against the one or more early termination box nodes, determining whether to end traversal of the bounding volume hierarchy and determine whether the ray intersects geometry for…
Memory management in graphics and compute application programming interfaces
Granted: December 6, 2022
Patent Number:
11521293
Methods are provided for creating objects in a way that permits an API client to explicitly participate in memory management for an object created using the API. Methods for managing data object memory include requesting memory requirements for an object using an API and expressly allocating a memory location for the object based on the memory requirements. Methods are also provided for cloning objects such that a state of the object remains unchanged from the original object to the…
Dedicated interface for coupling flash memory and dynamic random access memory
Granted: November 29, 2022
Patent Number:
11513689
The present application describes embodiments of an interface for coupling flash memory and dynamic random access memory (DRAM) in a processing system. Some embodiments include a dedicated interface between a flash memory and DRAM. The dedicated interface is to provide access to the flash memory in response to instructions received over a DRAM interface between the DRAM and a processing device. Some embodiments of a method include accessing a flash memory via a dedicated interface…
Controlling accesses to a branch prediction unit for sequences of fetch groups
Granted: November 29, 2022
Patent Number:
11513801
An electronic device is described that handles control transfer instructions (CTIs) when executing instructions in program code. The electronic device has a processor that includes a branch prediction functional block and a sequential fetch logic functional block. The sequential fetch logic functional block determines, based on a record associated with a CTI, that a specified number of fetch groups of instructions that were previously determined to include no CTIs are to be fetched for…
