Sense amplifier sleep state for leakage savings without bias mismatch
Granted: November 29, 2022
Patent Number:
11514956
A sense amplifier is biased to reduce leakage current equalize matched transistor bias during an idle state. A first read select transistor couples a true bit line and a sense amplifier true (SAT) signal line and a second read select transistor couples a complement bit line and a sense amplifier complement (SAC) signal line. The SAT and SAC signal lines are precharged during a precharge state. An equalization circuit shorts the SAT and SAC signal lines during the precharge state. A…
Secure and power efficient audio data processing
Granted: November 29, 2022
Patent Number:
11514194
Devices, methods, and systems for secure communications on a computing device. A host operating system (OS) runs on a host processor in communication with a host memory. A secure OS runs on a coprocessor in communication with a secure memory. The coprocessor receives information from an external device over a secure peer-to-peer (P2P) connection. The secure P2P connection is managed by the secure OS and is not accessible by the host OS.
Arbitration scheme for coherent and non-coherent memory requests
Granted: November 29, 2022
Patent Number:
11513973
A processor in a system is responsive to a coherent memory request buffer having a plurality of entries to store coherent memory requests from a client module and a non-coherent memory request buffer having a plurality of entries to store non-coherent memory requests from the client module. The client module buffers coherent and non-coherent memory requests and releases the memory requests based on one or more conditions of the processor or one of its caches. The memory requests are…
Controlling accesses to a branch prediction unit for sequences of fetch groups
Granted: November 29, 2022
Patent Number:
11513801
An electronic device is described that handles control transfer instructions (CTIs) when executing instructions in program code. The electronic device has a processor that includes a branch prediction functional block and a sequential fetch logic functional block. The sequential fetch logic functional block determines, based on a record associated with a CTI, that a specified number of fetch groups of instructions that were previously determined to include no CTIs are to be fetched for…
Data compression and encryption based on translation lookaside buffer evictions
Granted: November 22, 2022
Patent Number:
11507519
A processing system selectively compresses cache lines at a cache or at a memory or encrypts cache lines at the memory based on evictions of entries mapping virtual-to-physical address translations from a translation lookaside buffer (TLB). Upon eviction of a TLB entry, the processing system identifies cache lines corresponding to the physical addresses of the evicted TLB entry and selectively compresses the cache lines to increase the effective storage capacity of the processing system…
Masked fault detection for reliable low voltage cache operation
Granted: November 22, 2022
Patent Number:
11509333
Systems, apparatuses, and methods for implementing masked fault detection for reliable low voltage cache operation are disclosed. A processor includes a cache that can operate at a relatively low voltage level to conserve power. However, at low voltage levels, the cache is more likely to suffer from bit errors. To mitigate the bit errors occurring in cache lines at low voltage levels, the cache employs a strategy to uncover masked faults during runtime accesses to data by actual software…
Throttling hull shaders based on tessellation factors in a graphics pipeline
Granted: November 22, 2022
Patent Number:
11508124
A processing system includes hull shader circuitry that launches thread groups including one or more primitives. The hull shader circuitry also generates tessellation factors that indicate subdivisions of the primitives. The processing system also includes throttling circuitry that estimates a primitive launch time interval for the domain shader based on the tessellation factors and selectively throttles launching of the thread groups from the hull shader circuitry based on the primitive…
Temperature-based adjustments for in-memory matrix multiplication
Granted: November 22, 2022
Patent Number:
11507641
Techniques for performing in-memory matrix multiplication, taking into account temperature variations in the memory, are disclosed. In one example, the matrix multiplication memory uses ohmic multiplication and current summing to perform the dot products involved in matrix multiplication. One downside to this analog form of multiplication is that temperature affects the accuracy of the results. Thus techniques are provided herein to compensate for the effects of temperature increases on…
Active bridge chiplet with integrated cache
Granted: November 22, 2022
Patent Number:
11507527
A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via an active bridge chiplet. The active bridge chiplet is an active silicon die that bridges GPU chiplets and allows partitioning of systems-on-a-chip (SoC) functionality into smaller functional…
Memory request priority assignment techniques for parallel processors
Granted: November 22, 2022
Patent Number:
11507522
Systems, apparatuses, and methods for implementing memory request priority assignment techniques for parallel processors are disclosed. A system includes at least a parallel processor coupled to a memory subsystem, where the parallel processor includes at least a plurality of compute units for executing wavefronts in lock-step. The parallel processor assigns priorities to memory requests of wavefronts on a per-work-item basis by indexing into a first priority vector, with the index…
Scalable region-based directory
Granted: November 22, 2022
Patent Number:
11507517
Disclosed is a cache directory including one or more cache directories configurable to interchange within each cache directory entry at least one bit between a first field and a second field to change the size of the region of memory represented and the number of cache lines tracked in the cache subsystem.
Branch confidence throttle
Granted: November 22, 2022
Patent Number:
11507380
A processing system includes a processor with a branch predictor including one or more branch target buffer tables. The processor also includes a branch prediction pipeline including a throttle unit and an uncertainty accumulator. The processor assigns an uncertainty value for each of a plurality of branch predictions generated by the branch predictor and adds the uncertainty value for each of the plurality of branch predictions to an accumulated uncertainty counter associated with the…
Electrical design current throttling
Granted: November 22, 2022
Patent Number:
11507158
Electrical design current throttling, including: applying an electrical design current (EDC) threshold for each control processing unit component of a plurality of the central processing unit components responsive to the corresponding priority of each central processing unit component, the priority of a central processing unit component responsive to a central processing unit component's current usage data.
Method and apparatus for an HDR hardware processor inline to hardware encoder and decoder
Granted: November 15, 2022
Patent Number:
11503310
A device includes an encoder, decoder, codec or combination thereof and inline hardware conversion units that are operative to convert stored image data into one of: an HDR/WCG format and an SDR/SCG format during the conversion process. Each of the inline hardware conversion units is operative to perform the conversion process independent of another read operation with the memory that stores the image data to be converted. In one example, an encoding unit is operative to perform a write…
Region-based image compression and decompression
Granted: November 15, 2022
Patent Number:
11503295
An apparatus for encoding an image and an apparatus for decoding an image are presented. An image contains one or more regions. For encoding the image, the image is decomposed into one or more regions and a region is evaluated to determine whether the region meets a predetermined compressions acceptability criteria. The region is then encoded in response to the transformed and quantized region meeting the predetermined compression acceptability criteria. For decoding the image, a region…
Prefetch kernels on data-parallel processors
Granted: November 15, 2022
Patent Number:
11500778
Embodiments include methods, systems and non-transitory computer-readable computer readable media including instructions for executing a prefetch kernel with reduced intermediate state storage resource requirements. These include executing a prefetch kernel on a graphics processing unit (GPU), such that the prefetch kernel begins executing before a processing kernel. The prefetch kernel performs memory operations that are based upon at least a subset of memory operations in the…
Pipeline including separate hardware data paths for different instruction types
Granted: November 8, 2022
Patent Number:
11494192
A processing element is implemented in a stage of a pipeline and configured to execute an instruction. A first array of multiplexers is to provide information associated with the instruction to the processing element in response to the instruction being in a first set of instructions. A second array of multiplexers is to provide information associated with the instruction to the first processing element in response to the instruction being in a second set of instructions. A control unit…
Memory controller with a plurality of command sub-queues and corresponding arbiters
Granted: November 8, 2022
Patent Number:
11494316
A memory controller includes a memory channel controller that uses multiple groups of command queue and arbiter pairs. Each arbiter is coupled to a respective command queue to select memory access commands from each command queue according to predetermined criteria. Each arbiter selects from among the memory access requests in each command queue independently based on the predetermined criteria and sends selected memory access requests to a selector that serves as a second level arbiter…
Page table walker with page table entry (PTE) physical address prediction
Granted: November 8, 2022
Patent Number:
11494300
Methods and apparatus provide virtual to physical address translations and a hardware page table walker with region based page table prefetch operation that produces virtual memory region tracking information that includes at least: data representing a virtual base address of a virtual memory region and a physical address of a first page table entry (PTE) corresponding to a virtual page within the virtual memory region. The hardware page table walker, in response to the TLB miss…
Domain identifier and device identifier translation by an input-output memory management unit
Granted: November 8, 2022
Patent Number:
11494211
An electronic device includes a processor that executes a guest operating system and a hypervisor, an input-output (IO) device, and an input-output memory management unit (IOMMU). The IOMMU handles communications between the IOMMU and the guest operating system by: replacing, in communications received from the guest operating system, guest domain identifiers (domainIDs) with corresponding host domainIDs and/or guest device identifiers (deviceIDs) with corresponding host deviceIDs before…
