Cooperative workgroup scheduling and context prefetching based on predicted modification of signal values
Granted: October 25, 2022
Patent Number:
11481250
A first workgroup is preempted in response to threads in the first workgroup executing a first wait instruction including a first value of a signal and a first hint indicating a type of modification for the signal. The first workgroup is scheduled for execution on a processor core based on a first context after preemption in response to the signal having the first value. A second workgroup is scheduled for execution on the processor core based on a second context in response to…
Atomic operations in a large scale distributed computing network
Granted: October 25, 2022
Patent Number:
11481216
Techniques for executing an atomic command in a distributed computing network are provided. A core cluster, including a plurality of processing cores that do not natively issue atomic commands to the distributed computing network, is coupled to a translation unit. To issue an atomic command, a core requests a location in the translation unit to write an opcode and operands for the atomic command. The translation unit identifies a location (a “window”) that is not in use by another…
Dual purpose millimeter wave frequency band transmitter
Granted: October 25, 2022
Patent Number:
11480672
Systems, apparatuses, and methods for implementing a dual-purpose millimeter-wave frequency band transmitter are disclosed. A system includes a dual-purpose transmitter sending a video stream over a wireless link to a receiver. In some embodiments, the video stream is generated as part of an augmented reality (AR) or virtual reality (VR) application. The transmitter operates in a first mode to scan and map an environment of the transmitter and receiver. The transmitter generates radio…
Activation function functional block for electronic devices
Granted: October 18, 2022
Patent Number:
11475305
An electronic device has an activation function functional block that implements an activation function. During operation, the activation function functional block receives an input including a plurality of bits representing a numerical value. The activation function functional block then determines a range from among a plurality of ranges into which the input falls, each range including a separate portion of possible numerical values of the input. The activation function functional…
Supporting responses for memory types with non-uniform latencies on same channel
Granted: October 18, 2022
Patent Number:
11474942
Systems, apparatuses, and methods for identifying response data arriving out-of-order from two different memory types are disclosed. A computing system includes one or more clients for processing applications. A memory channel transfers memory traffic between a memory controller and a memory bus connected to each of a first memory and a second memory different from the first memory. The memory controller determines a given point in time when read data is to be scheduled to arrive on the…
Refresh management for DRAM
Granted: October 18, 2022
Patent Number:
11474746
A memory controller interfaces with a dynamic random access memory (DRAM). The memory controller selectively places memory commands in a memory interface queue and transmits the memory commands from the memory interface queue to a memory channel coupled to at least one dynamic random access memory (DRAM). An activate counter is maintained related to a number of activate commands sent over the memory channel to a memory region of the DRAM. In response to the activate counter being at or…
Memory system with region-specific memory access scheduling
Granted: October 18, 2022
Patent Number:
11474703
An integrated circuit device includes a memory controller coupleable to a memory. The memory controller to schedule memory accesses to regions of the memory based on memory timing parameters specific to the regions. A method includes receiving a memory access request at a memory device. The method further includes accessing, from a timing data store of the memory device, data representing a memory timing parameter specific to a region of the memory cell circuitry targeted by the memory…
Semiconductor chip with redundant thru-silicon-vias
Granted: October 11, 2022
Patent Number:
11469212
A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.
Graded throttling for network-on-chip traffic
Granted: October 11, 2022
Patent Number:
11470004
Graded throttling for network-on-chip traffic, including: calculating, by an agent of a network-on-chip, a number of outstanding transactions issued by the agent; determining that the number of outstanding transactions meets a threshold; and implementing, by the agent, in response to the number of outstanding transactions meeting the threshold, a traffic throttling policy.
High speed transmitter
Granted: October 11, 2022
Patent Number:
11469760
A single stage transmitter that operates at high speed is configured to operate as a driver in write mode and a termination in read mode. The driver configuration includes two circuits. The first circuit includes a PMOS cross-coupled device and a PMOS cascode circuit. The second circuit includes a NMOS cross-coupled device and a NMOS cascode circuit. The PMOS cross-coupled device and the NMOS cross-coupled device is connected in series by alternating current (AC) coupling capacitors. The…
Multirow semiconductor chip connections
Granted: October 11, 2022
Patent Number:
11469183
A method of manufacturing a semiconductor device includes mounting an interconnect chip to a redistribution layer structure and mounting a first, second, and third semiconductor chip to the redistribution layer structure, where the second semiconductor chip is interposed between the first and the third semiconductor chips, and the interconnect chip communicatively couples the first, second and third, semiconductor chips to one another.
Processing-in-memory concurrent processing system and method
Granted: October 11, 2022
Patent Number:
11468001
A processing system includes a processing unit and a memory device. The memory device includes a processing-in-memory (PIM) module that performs processing operations on behalf of the processing unit. An instruction set architecture (ISA) of the PIM module has fewer instructions than an ISA of the processing unit. Instructions received from the processing unit are translated such that processing resources of the PIM module are virtualized. As a result, the PIM module concurrently…
Configuring cache policies for a cache based on combined cache policy testing
Granted: October 11, 2022
Patent Number:
11467937
An electronic device includes a cache with a cache controller and a cache memory. The electronic device also includes a cache policy manager. The cache policy manager causes the cache controller to use two or more cache policies for cache operations in each of multiple test regions in the cache memory, with different configuration values for the two or more cache policies being used in each test region. The cache policy manager selects a selected configuration value for at least one…
VMID as a GPU task container for virtualization
Granted: October 11, 2022
Patent Number:
11467870
Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the…
Fastpath microcode sequencer
Granted: October 11, 2022
Patent Number:
11467838
Systems, apparatuses, and methods for implementing a fastpath microcode sequencer are disclosed. A processor includes at least an instruction decode unit and first and second microcode units. For each received instruction, the instruction decode unit forwards the instruction to the first microcode unit if the instruction satisfies at least a first condition. In one implementation, the first condition is the instruction being classified as a frequently executed instruction. If a received…
Compiler operations for heterogeneous code objects
Granted: October 11, 2022
Patent Number:
11467812
Described herein are techniques for performing compilation operations for heterogeneous code objects. According to the techniques, a compiler identifies architectures targeted by a compilation unit, compiles the compilation unit into a heterogeneous code object that includes a different code object portion for each identified architecture, performs name mangling on functions of the compilation unit, links the heterogeneous code object with a second code object to form an executable, and…
Selecting a low power state in an electronic device
Granted: October 11, 2022
Patent Number:
11467650
The described embodiments include an electronic device that has a hardware controller and one or more hardware subsystems. The one or more hardware subsystems support an active state, a first low power state, and a second low power state. The first low power state and second low power states are separate low power states, with the first low power state being associated with a more rapid resumption of the active state than the second low power state. The hardware controller is configured…
System and method for controlling electrical current supply in a multi-processor core system via instruction per cycle reduction
Granted: October 4, 2022
Patent Number:
11460879
Methods and apparatuses control electrical current supplied to a plurality of processing units in a multi-processor system. A plurality of current usage information corresponding to the processing units are received by a controller to determine a threshold current for each of the processing units. The controller determines a frequency reduction action and an instructions-per-cycle (IPC) reduction action for the each of the processing units based on the threshold current and regulates…
Level shifting output circuit
Granted: October 4, 2022
Patent Number:
11463084
A level shifting output circuit converts a signal from a core voltage to an I/O voltage without causing voltage overstress on transistor terminals in the level shifting output circuit. The output circuit includes protection transistors to protect various transistors in the output circuit from overvoltage conditions including those transistors coupled to I/O power supply nodes.
Platform agnostic atomic operations
Granted: October 4, 2022
Patent Number:
11461045
A processing unit is configured to access a first memory that supports atomic operations and a second memory via an interface. The second memory or the interface does not support atomicity of the atomic operations. A trap handler is configured to trap atomic operations and enforce atomicity of the trapped atomic operations. The processing unit selectively provides atomic operations to the trap handler in response to detecting that memory access requests in the atomic operations are…
