Circuit board with compact passive component arrangement
Granted: November 8, 2022
Patent Number:
11495588
Various circuit boards with mounted passive components and method of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes at least partially encapsulating a first plurality of passive components in a molding material to create a first molded passive component group. The first molded passive component group is mounted on a surface of a circuit board. The first plurality of passive components are electrically connected to the circuit board.
Fuses to measure electrostatic discharge during die to substrate or package assembly
Granted: November 8, 2022
Patent Number:
11495535
A system and method for detecting and measuring electrostatic discharge during semiconductor assembly are described. A semiconductor device fabrication process forms a conductor between two metal routes in a series path on a semiconductor die. The series path is between a bump on the die and a substrate tie. The two metal routes have a width greater than a threshold based on a metal width capable of conducting a critical current density caused by an electrostatic discharge event without…
Uninhibited cooling path solution for active thermal control in device testing
Granted: November 8, 2022
Patent Number:
11495478
Systems, apparatuses, and methods for efficiently performing active thermal control during device testing are disclosed. A device testing system includes a device under test, a thermal structure on top of the device under test, and a controller configured to determine when to apply and remove thermal energy to the device under test through the thermal structure. The thermal structure includes a thermal transfer block that transfers thermal energy to and from the device under test below…
Tiling format for convolutional neural networks
Granted: November 8, 2022
Patent Number:
11494592
Systems, apparatuses, and methods for converting data to a tiling format when implementing convolutional neural networks are disclosed. A system includes at least a memory, a cache, a processor, and a plurality of compute units. The memory stores a first buffer and a second buffer in a linear format, where the first buffer stores convolutional filter data and the second buffer stores image data. The processor converts the first and second buffers from the linear format to third and…
Memory controller with a plurality of command sub-queues and corresponding arbiters
Granted: November 8, 2022
Patent Number:
11494316
A memory controller includes a memory channel controller that uses multiple groups of command queue and arbiter pairs. Each arbiter is coupled to a respective command queue to select memory access commands from each command queue according to predetermined criteria. Each arbiter selects from among the memory access requests in each command queue independently based on the predetermined criteria and sends selected memory access requests to a selector that serves as a second level arbiter…
Page table walker with page table entry (PTE) physical address prediction
Granted: November 8, 2022
Patent Number:
11494300
Methods and apparatus provide virtual to physical address translations and a hardware page table walker with region based page table prefetch operation that produces virtual memory region tracking information that includes at least: data representing a virtual base address of a virtual memory region and a physical address of a first page table entry (PTE) corresponding to a virtual page within the virtual memory region. The hardware page table walker, in response to the TLB miss…
Automatic data format detection
Granted: November 1, 2022
Patent Number:
11488328
Systems, apparatuses, and methods for implementing automatic data format detection techniques are disclosed. A graphics engine receives data of indeterminate format and the graphics engine predicts an organization of the data. As part of the prediction, the graphics engine predicts the pixel depth (i.e., bytes per pixel (BPP)) and format separately. The graphics engine folds the data along pixel and channel boundaries to help in determining the pixel depth and format. The graphics engine…
Back side metallization
Granted: November 1, 2022
Patent Number:
11488922
An integrated circuit device wafer includes a silicon wafer substrate and a back side metallization structure. The back side metallization structure includes a first adhesion layer on the back side of the substrate, a first metal later over the first adhesion layer, a second metal layer over the first metal layer, and a second adhesion layer over the second metal layer. The first includes at least one of: silicon nitride and silicon dioxide. The first metal layer includes titanium. The…
Memory row recording for mitigating crosstalk in dynamic random access memory
Granted: November 1, 2022
Patent Number:
11488654
A method includes adding a set of one or more victim rows to a first probabilistic filter and to a second probabilistic filter, in response to a memory access request, identifying a candidate victim row adjacent to a memory address specified by a memory access request, identifying the candidate victim row as a victim row in the set of victim rows based on performing a lookup of the candidate victim row in a selected filter, where the selected filter includes one of the first…
Mechanism for supporting discard functionality in a ray tracing context
Granted: November 1, 2022
Patent Number:
11488343
Described herein is a technique for performing ray tracing. According to this technique, instead of executing intersection and/or any hit shaders during traversal of an acceleration structure to determine the closest hit for a ray, an acceleration structure is fully traversed in an invocation of a shader program, and the closest intersection with a triangle is recorded in a data structure associated with the material of the triangle. Later, a scheduler launches waves by grouping together…
GPU cache management based on locality type detection
Granted: November 1, 2022
Patent Number:
11487671
Wavefront loading in a processor is managed and includes monitoring a selected wavefront of a set of wavefronts. Reuse of memory access requests for the selected wavefront is counted. A cache hit rate in one or more caches of the processor is determined based on the counted reuse. Based on the cache hit rate, subsequent memory requests of other wavefronts of the set of wavefronts are modified by including a type of reuse of cache lines in requests to the caches. In the caches, storage of…
Preemptive signal integrity control
Granted: November 1, 2022
Patent Number:
11487605
Techniques are provided herein for pre-emptively reinforcing one or more buses of a computing device against the effects of signal noise that could cause a reduction in signal integrity. The techniques generally include detecting an event (or “trigger”) that would tend to indicate that a reduction in signal integrity will occur, examining a reinforcement action policy and system status to determine what reinforcement action to take, and performing the reinforcement action.
Hardware-software collaborative address mapping scheme for efficient processing-in-memory systems
Granted: November 1, 2022
Patent Number:
11487447
Approaches are provided for implementing hardware-software collaborative address mapping schemes that enable mapping data elements which are accessed together in the same row of one bank or over the same rows of different banks to achieve higher performance by reducing row conflicts. Using an intra-bank frame striping policy (IBFS), corresponding subsets of data elements are interleaved into a single row of a bank. Using an intra-channel frame striping policy (ICFS), corresponding…
Probe filter retention based low power state
Granted: November 1, 2022
Patent Number:
11487340
A data fabric routes requests between the plurality of requestors and the plurality of responders. The data fabric includes a crossbar router, a coherent slave controller coupled to the crossbar router, and a probe filter coupled to the coherent slave controller and tracking the state of cached lines of memory. Power state control circuitry operates, responsive to detecting any of a plurality of designated conditions, to cause the probe filter to enter a retention low power state in…
Dual purpose millimeter wave frequency band transmitter
Granted: October 25, 2022
Patent Number:
11480672
Systems, apparatuses, and methods for implementing a dual-purpose millimeter-wave frequency band transmitter are disclosed. A system includes a dual-purpose transmitter sending a video stream over a wireless link to a receiver. In some embodiments, the video stream is generated as part of an augmented reality (AR) or virtual reality (VR) application. The transmitter operates in a first mode to scan and map an environment of the transmitter and receiver. The transmitter generates radio…
Forward progress mechanisms for a communications network having multiple nodes
Granted: October 25, 2022
Patent Number:
11483209
A communication network includes: a plurality of nodes in a topology, with each node having an upstream and a downstream neighboring node in the topology; a separate unidirectional communication link coupled between each node and that node's downstream neighboring node; and a separate unidirectional control link coupled between each node and that node's upstream neighboring node. A controller in each node keeps a count of packets sent by that node via the corresponding unidirectional…
Command processor based multi dispatch scheduler
Granted: October 25, 2022
Patent Number:
11481953
Described herein are techniques for performing ray tracing operations. A command processor executes custom instructions for orchestrating a ray tracing pipeline. The custom instructions cause the command processor to perform a series of loop iterations, each at a particular recursion depth. In a first loop iteration, a ray generation shader is executed that triggers execution of a trace ray operation. In any other iteration, zero or more shaders are executed based on the contents of a…
Task graph scheduling for workload processing
Granted: October 25, 2022
Patent Number:
11481256
Techniques for scheduling operations for a task graph on a processing device are provided. The techniques include receiving a task graph that specifies one or more passes, one or more resources, and one or more directed edges between passes and resources; identifying independent passes and dependent passes of the task graph; based on performance criteria of the processing device, scheduling commands to execute the passes; and transmitting scheduled commands to the processing device for…
Cooperative workgroup scheduling and context prefetching based on predicted modification of signal values
Granted: October 25, 2022
Patent Number:
11481250
A first workgroup is preempted in response to threads in the first workgroup executing a first wait instruction including a first value of a signal and a first hint indicating a type of modification for the signal. The first workgroup is scheduled for execution on a processor core based on a first context after preemption in response to the signal having the first value. A second workgroup is scheduled for execution on the processor core based on a second context in response to…
Atomic operations in a large scale distributed computing network
Granted: October 25, 2022
Patent Number:
11481216
Techniques for executing an atomic command in a distributed computing network are provided. A core cluster, including a plurality of processing cores that do not natively issue atomic commands to the distributed computing network, is coupled to a translation unit. To issue an atomic command, a core requests a location in the translation unit to write an opcode and operands for the atomic command. The translation unit identifies a location (a “window”) that is not in use by another…
