Arrangement and thermal management of 3D stacked dies
Granted: November 2, 2021
Patent Number:
11164807
Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.
System probe aware last level cache insertion bypassing
Granted: November 2, 2021
Patent Number:
11163688
Systems, apparatuses, and methods for employing system probe filter aware last level cache insertion bypassing policies are disclosed. A system includes a plurality of processing nodes, a probe filter, and a shared cache. The probe filter monitors a rate of recall probes that are generated, and if the rate is greater than a first threshold, then the system initiates a cache partitioning and monitoring phase for the shared cache. Accordingly, the cache is partitioned into two portions. If…
Bounding volume hierarchy generation
Granted: October 26, 2021
Patent Number:
11158112
Techniques for performing ray tracing operations are provided. The techniques include identifying bounding-box-surface-area-weighted centroid of a group of primitives associated with a bounding box of a bounding volume hierarchy (“BVH”); generating candidate splits at the centroid, the candidate splits defining geometry subgroups; identifying a candidate split having a lowest surface area bounding box; and generating nodes for the BVH that include geometry of the geometry subgroups…
VRS rate feedback
Granted: October 26, 2021
Patent Number:
11158106
Techniques for performing shader operations are provided. The techniques include, performing pixel shading at a shading rate defined by pixel shader variable rate shading (“VRS”) data, updating the pixel VRS data that indicates one or more shading rates for one or more tiles based on whether the tiles of the one or more tiles include triangle edges or do not include triangle edges, to generate updated VRS data, and writing a VRS rate feedback buffer based on the updated VRS data.
Hybrid first-fit K-choice insertions for hash tables, hash sets, approximate set membership data structures, and caches
Granted: October 26, 2021
Patent Number:
11157174
A hybrid mechanism for operating on a data item in connection with an associative structure combines first-fit and K-choice. The hybrid mechanism leverages advantages of both approaches by choosing whether to insert, retrieve, delete, or modify a data item using either first-fit or K-choice. Based on the data item, a function of the data item, and/or other factors such as the load statistics of the associative structure, one of either first-fit or K-choice is used to improve operation on…
Termination calibration scheme using a current mirror
Granted: October 19, 2021
Patent Number:
11152944
Systems, apparatuses, and methods for conveying and receiving information as electrical signals in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination…
Data communications with enhanced speed mode
Granted: October 19, 2021
Patent Number:
11151075
An interconnect controller includes a data link layer controller coupled to a transaction layer, wherein the data link layer controller selectively receives data packets from and sends data packets to the transaction layer, and a physical layer controller coupled to the data link layer controller and to a communication link. The physical layer controller selectively operates at a first predetermined link speed. The physical layer controller has an enhanced speed mode, wherein in response…
Selecting a precision level for executing a workload in an electronic device
Granted: October 19, 2021
Patent Number:
11150899
An electronic device includes a controller functional block and a computational functional block. During operation, while the computational functional block executes a test portion of a workload at at least one precision level, the controller functional block monitors a behavior of the computational functional block. Based on the behavior of the computational functional block while executing the test portion of the workload at the at least one precision level, the controller functional…
Soft watermarking in thread shared resources implemented through thread mediation
Granted: October 12, 2021
Patent Number:
11144353
Techniques for use in a microprocessor core for soft watermarking in thread shared resources implemented through thread mediation. A thread is removed from a thread mediation decision involving multiple threads competing or requesting to use a shared resource at a current clock cycle based on a number of entries in the shared resource that the thread is estimated to have allocated to it at the current clock cycle. By removing the thread from the thread mediation decision, the thread is…
Quality of service for input/output memory management unit
Granted: October 12, 2021
Patent Number:
11144473
A data processing system includes a memory, a group of input/output (I/O) devices, an input/output memory management unit (IOMMU). The IOMMU is connected to the memory and adapted to allocate a hardware resource from among a group of hardware resources to receive an address translation request for a memory access from an I/O device. The IOMMU detects address translation requests from the plurality of I/O devices. The IOMMU reorders the address translation requests such that an order of…
Processor microcode with embedded jump table
Granted: October 12, 2021
Patent Number:
11144329
A processing unit employs microcode wherein the jump table associated with the microcode is embedded in the microcode itself. When the microcode is compiled based on a set of programmer instructions, the compiler prepares the jump table for the microcode and stores the jump table in the same file or other storage unit as the microcode. When the processing unit is initialized to execute a program, such as an operating system, the processing unit retrieves the microcode corresponding to…
Retire queue compression
Granted: October 12, 2021
Patent Number:
11144324
Systems, apparatuses, and methods for compressing multiple instruction operations together into a single retire queue entry are disclosed. A processor includes at least a scheduler, a retire queue, one or more execution units, and control logic. When the control logic detects a given instruction operation being dispatched by the scheduler to an execution unit, the control logic determines if the given instruction operation meets one or more conditions for being compressed with one or…
Data compression system using base values and methods thereof
Granted: October 12, 2021
Patent Number:
11144208
In some embodiments, a memory controller in a processor includes a base value cache, a compressor, and a metadata cache. The compressor is coupled to the base value cache and the metadata cache. The compressor compresses a data block using at least a base value and delta values. The compressor determines whether the size of the data block exceeds a data block threshold value. Based on the determination of whether the size of the compressed data block generated by the compressor exceeds…
Analysis of electro-optic waveforms
Granted: October 12, 2021
Patent Number:
11143700
An optic probe is used to measure signals from a device under test. The optic probe is positioned at a target probe location within a cell of the device under test, the cell including a target net to be measured and a plurality of non-target nets. A test pattern is applied to the cell with the optic probe a laser probe (LP) waveform is obtained in response. A target net waveform is extracted from the LP waveform by: (i) simulating a combinational logic analysis (CLA) cross-talk waveform…
Custom beamforming during a vertical blanking interval
Granted: October 5, 2021
Patent Number:
11140368
Systems, apparatuses, and methods for scheduling beamforming training during vertical blanking intervals (VBIs) are disclosed. A system includes a transmitter sending a video stream over a wireless link to a receiver. The wireless link between the transmitter and the receiver has capacity characteristics that fluctuate with variations in the environment. To combat the fluctuating capacity characteristics of the link, the transmitter and the receiver perform periodic beamforming training…
System and method of managing electronic meeting invitations
Granted: October 5, 2021
Patent Number:
11140107
Various messaging systems and methods are disclosed for meeting invitation management. In one aspect, a method of messaging is provided that includes generating a message to invite one or more invitees to a meeting. The message includes an assertion to suppress an auto-responder of the one or more invitees. The message is sent to the one or more invitees. The assertion suppresses the auto-responder of the one or more invitees.
Spatial pipelining of software reductions and scans
Granted: October 5, 2021
Patent Number:
11138015
A compute unit includes single-instruction-multiple-data (SIMD) lanes that implement a pipeline. The compute unit also includes a scheduler to schedule the SIMD lanes to apply a binary associative operation to pairs of elements associated with ordered sets of elements. Subsets of the SIMD lanes concurrently apply the binary associative operation to pairs of elements at different levels of upsweep trees associated with the ordered sets of elements. Application of the binary associative…
Command replay for non-volatile dual inline memory modules
Granted: October 5, 2021
Patent Number:
11137941
Memory access commands are placed in a memory interface queue and transmitted from the memory interface queue to a heterogeneous memory channel coupled to a volatile dual in-line memory module (DIMM) and a non-volatile DIMM. Selected memory access commands that are placed in the memory interface queue are stored in a replay queue. The non-volatile reads that are placed in the memory interface queue are in a non-volatile command queue (NV queue). The method detects, based on information…
Runtime localized cooling of high-performance processors
Granted: October 5, 2021
Patent Number:
11137809
A plurality of thermal electric cooler (TEC) elements are formed in a TEC grid structure. Control logic dynamically varies a supply current supplied to each TEC element (or group of TEC elements) in the TEC grid based on changes in power density respectively associated with areas cooled by each of the TEC elements or group of TEC elements.
Aggregated doorbells for unmapped queues in a graphics processing unit
Granted: September 28, 2021
Patent Number:
11132204
A processing system includes a set of queues to store command buffers prior to execution in a corresponding plurality of pipelines. The processing system also includes one or more first doorbells and a second doorbell. The first doorbells map to one or more queues in the set of queues on a one-to-one basis. The second doorbell maps to a subset of the set of queues on a one-to-many basis. A doorbell monitor generates an interrupt in response to an empty queue in the subset becoming a…
