Method and apparatus for physical layer bypass
Granted: September 28, 2021
Patent Number:
11132327
A method and apparatus for physical layer bypass data transmission between physical coding sub-layers (PCS) includes encoding the data for transmission over a serial low-speed link. The data is transmitted from a first PCS via a serial connection over a serializer/deserializer (SERDES) transmission bypass path The data is received by a second PCS via a SERDES receive bypass path.
Aggregated doorbells for unmapped queues in a graphics processing unit
Granted: September 28, 2021
Patent Number:
11132204
A processing system includes a set of queues to store command buffers prior to execution in a corresponding plurality of pipelines. The processing system also includes one or more first doorbells and a second doorbell. The first doorbells map to one or more queues in the set of queues on a one-to-one basis. The second doorbell maps to a subset of the set of queues on a one-to-many basis. A doorbell monitor generates an interrupt in response to an empty queue in the subset becoming a…
Electro-optic waveform analysis process
Granted: September 21, 2021
Patent Number:
11125815
A reconfigurable optic probe is used to measure signals from a device under test. The reconfigurable optic probe is positioned at a target probe location within a cell of the device under test. The cell including a target net to be measured and non-target nets. A test pattern is applied to the cell and a laser probe (LP) waveform is obtained in response. A target net waveform is extracted from the LP waveform by: i) configuring the reconfigurable optic probe to produce a ring-shaped beam…
Dynamic voltage and frequency scaling based on memory channel slack
Granted: September 14, 2021
Patent Number:
11119665
A processing system scales power to memory and memory channels based on identifying causes of stalls of threads of a wavefront. If the cause is other than an outstanding memory request, the processing system throttles power to the memory to save power. If the stall is due to memory stalls for a subset of the memory channels servicing memory access requests for threads of a wavefront, the processing system adjusts power of the memory channels servicing memory access request for the…
Method and apparatus for color gamut mapping color gradient preservation
Granted: September 14, 2021
Patent Number:
11120725
A method and apparatus for gamut mapping color gradient preservation is described. In one example, the method and apparatus obtains a source image having a plurality of source color gamut pixels in a source color gamut, wherein the plurality of source color gamut pixels include a same hue value and a same luminance value and define a color gradient, and converts the plurality of source color gamut pixels to a plurality of target color gamut pixels such that the color gradient of the…
Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level
Granted: September 14, 2021
Patent Number:
11120190
A system and method for laying out power grid connections for standard cells are described. In various embodiments, a standard cell includes power post and ground posts in metal zero. The metal zero posts include no vias to any upper metal layers. Some variations of the standard cell have the power and ground posts routed in metal zero to a boundary edge of the standard cell. Layout rules are changed to allow this type of routing. The power and ground posts in metal zero are connected to…
Memory pools in a memory model for a unified computing system
Granted: September 14, 2021
Patent Number:
11119944
A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a plurality of processors. The method includes receiving a memory operation from a processor that receives a memory operation from a processor that references an address in a shared memory, mapping the received memory operation to at least one of a plurality of virtual memory pools to produce a mapping result, and providing the mapping result to the processor.
Region based directory scheme to adapt to large cache sizes
Granted: September 14, 2021
Patent Number:
11119926
Systems, apparatuses, and methods for maintaining a region-based cache directory are disclosed. A system includes multiple processing nodes, with each processing node including a cache subsystem. The system also includes a cache directory to help manage cache coherency among the different cache subsystems of the system. In order to reduce the number of entries in the cache directory, the cache directory tracks coherency on a region basis rather than on a cache line basis, wherein a…
Locality-aware and sharing-aware cache coherence for collections of processors
Granted: September 14, 2021
Patent Number:
11119923
A cache coherence technique for operating a multi-processor system including shared memory includes allocating a cache line of a cache memory of a processor to a memory address in the shared memory in response to execution of an instruction of a program executing on the processor. The technique includes encoding a shared information state of the cache line to indicate whether the memory address is a shared memory address shared by the processor and a second processor, or a private memory…
Computing system with wireless debug code output
Granted: September 14, 2021
Patent Number:
11119893
Various computing systems and methods of using the same are disclosed. In one aspect, a computing system is provided that includes a semiconductor chip that is operable to execute start up self test code. An encoder is operable to encode the progress of the execution of the start up self test code to generate encoded debug code. Also included is means for wirelessly outputting the encoded debug code from the computing system.
Machine intelligence performance boost with energy reservoir
Granted: September 14, 2021
Patent Number:
11119549
Control of power supplied to a machine intelligence (MI) processor is provided with an energy reservoir and power switching circuitry coupled to a power supply, the energy reservoir, and to power delivery circuitry of the MI processor. Control circuitry directs the power switching circuitry to charge the energy reservoir from the power supply or discharge the energy reservoir to the MI processor based on MI state information obtained from the MI processor. Processes for charging and…
Source clock recovery in wireless video systems
Granted: September 7, 2021
Patent Number:
11115693
Systems, apparatuses, and methods for performing efficient video transmission are disclosed. In a video processing system, a transmitter sends encoded pixel data to a receiver. The receiver stores the encoded pixel data in a buffer at an input data rate. A decoder of the receiver reads the pixel data from the buffer at an output data rate. Each of a transmitter and the receiver maintains a respective synchronization counter. When detecting a start of a frame, each of the transmitter and…
Speculative instruction wakeup to tolerate draining delay of memory ordering violation check buffers
Granted: September 7, 2021
Patent Number:
11113065
A technique for speculatively executing load-dependent instructions includes detecting that a memory ordering consistency queue is full for a completed load instruction. The technique also includes storing data loaded by the completed load instruction into a storage location for storing data when the memory ordering consistency queue is full. The technique further includes speculatively executing instructions that are dependent on the completed load instruction. The technique also…
Register saving for function calling
Granted: September 7, 2021
Patent Number:
11113061
Described herein are techniques for saving registers in the event of a function call. The techniques include modifying a program including a block of code designated as a calling code that calls a function. The modifying includes modifying the calling code to set a register usage mask indicating which registers are in use at the time of the function call. The modifying also includes modifying the function to combine the information of the register usage mask with information indicating…
Techniques for performing store-to-load forwarding
Granted: September 7, 2021
Patent Number:
11113056
A technique for performing store-to-load forwarding is provided. The technique includes determining a virtual address for data to be loaded for the load instruction, identifying a matching store instruction from one or more store instruction memories by comparing a virtual-address-based comparison value for the load instruction to one or more virtual-address-based comparison values of one or more store instructions, determining a physical address for the load instruction, and validating…
User interface system for display scaling events
Granted: September 7, 2021
Patent Number:
11112926
Systems, apparatuses, and methods for implementing enhanced scaling techniques for display objects are disclosed. When graphical content is created by an application, display objects register with a scaling manager to be notified of display scaling events. These display scaling events can be caused by changing displays, changing resolution or other parameters on a display, changing a text size, resizing one or more graphical elements, or otherwise. When a display scaling event is…
Quality of service dirty line tracking
Granted: August 31, 2021
Patent Number:
11106594
Systems, apparatuses, and methods for generating a measurement of write memory bandwidth are disclosed. A control unit monitors writes to a cache hierarchy. If a write to a cache line is a first time that the cache line is being modified since entering the cache hierarchy, then the control unit increments a write memory bandwidth counter. Otherwise, if the write is to a cache line that has already been modified since entering the cache hierarchy, then the write memory bandwidth counter…
Oscillator calibration
Granted: August 31, 2021
Patent Number:
11108382
An oscillator circuit includes a first oscillator, a second oscillator, and a calibration circuit to calibrate the first and second oscillators. The first oscillator is supplied with a first supply voltage, and the second oscillator is supplied with a second supply voltage. The calibration includes setting a frequency control of the second oscillator at a target frequency. Then, a voltage control of the second supply voltage is adjusted incrementally until a first control value is…
Cache replacement based on translation lookaside buffer evictions
Granted: August 31, 2021
Patent Number:
11106600
A processing system adjusts a cache replacement priority of cache lines at a cache based on evictions of entries mapping virtual-to-physical address translations from a translation lookaside buffer (TLB). Upon eviction of a TLB entry, the processing system identifies cache lines corresponding to the physical addresses of the evicted TLB entry and evicts the cache lines or adjusts the cache replacement priority of the cache lines so that their eviction from the cache will be accelerated.
Configurable skewed associativity in a translation lookaside buffer
Granted: August 31, 2021
Patent Number:
11106596
Methods, devices, and systems for determining an address in a physical memory which corresponds to a virtual address using a skewed-associative translation lookaside buffer (TLB) are described. A virtual address and a configuration indication are received using receiver circuitry. A physical address corresponding to the virtual address is output if a TLB hit occurs. A first subset of a plurality of ways of the TLB is configured to hold a first page size. The first subset includes a…
