Multiple application cooperative frame-based GPU scheduling
Granted: August 24, 2021
Patent Number:
11100604
Systems, apparatuses, and methods for scheduling jobs for multiple frame-based applications are disclosed. A computing system executes a plurality of frame-based applications for generating pixels for display. The applications convey signals to a scheduler to notify the scheduler of various events within a given frame being rendered. The scheduler adjusts the priorities of applications based on the signals received from the applications. The scheduler attempts to adjust priorities of…
Shared virtual address space for heterogeneous processors
Granted: August 24, 2021
Patent Number:
11100004
A processor uses the same virtual address space for heterogeneous processing units of the processor. The processor employs different sets of page tables for different types of processing units, such as a CPU and a GPU, wherein a memory management unit uses each set of page tables to translate virtual addresses of the virtual address space to corresponding physical addresses of memory modules associated with the processor. As data is migrated between memory modules, the physical addresses…
Apparatus and method for resynchronization prediction with variable upgrade and downgrade capability
Granted: August 24, 2021
Patent Number:
11099846
A method and apparatus generates control information that indicates whether to change a counter value associated with a particular load instruction. In response to the control information, the method and apparatus causes a hysteresis effect for operating between a speculative mode and a non-speculative mode based on the counter value. The hysteresis effect is in favor of the non-speculative mode. The method and apparatus causes the hysteresis effect by incrementing the counter value…
Near-memory data reduction
Granted: August 24, 2021
Patent Number:
11099788
An approach is provided for implementing near-memory data reduction during store operations to off-chip or off-die memory. A Near-Memory Reduction (NMR) unit provides near-memory data reduction during write operations to a specified address range. The NMR unit is configured with a range of addresses to be reduced and when a store operation specifies an address within the range of addresses, the NRM unit performs data reduction by adding the data value specified by the store operation to…
Signaling for heterogeneous memory systems
Granted: August 24, 2021
Patent Number:
11099786
A memory controller interfaces with a non-volatile storage class memory (SCM) module over a heterogeneous memory channel, and includes a command queue for receiving memory access commands. A memory interface queue is coupled to the command queue for holding outgoing commands. A non-volatile command queue is coupled to the command queue for storing non-volatile read commands that are placed in the memory interface queue. An arbiter selects entries from the command queue, and places them…
Bandwidth saving architecture for scalable video coding
Granted: August 17, 2021
Patent Number:
11095910
A system and method for scalable video coding that includes base layer having lower resolution encoding, enhanced layer having higher resolution encoding and the data transferring between two layers. The system and method provides several methods to reduce bandwidth of inter-layer transfers while at the same time reducing memory requirements. Due to less memory access, the system clock frequency can be lowered so that system power consumption is lowered as well. The system avoids having…
Pre-discharged bypass flip-flop circuit
Granted: August 17, 2021
Patent Number:
11095274
A pre-discharged edge-triggered flip-flop, in which internal nodes determinative of an output signal are discharged to VSS prior to an evaluation phase of a clock signal, is provided to enable improved clock-to-output response times when provided with a rising edge of a clock pulse. In operation, during a pre-discharge phase of the clock signal, multiple internal nodes of a differential master latch circuit of the flip-flop are discharged to VSS. In response to a rising edge of the clock…
Method of debugging a processor
Granted: August 17, 2021
Patent Number:
11093676
Methods for debugging a processor based on executing a randomly created and randomly executed executable on a fabricated processor. The executable may execute via startup firmware. By implementing randomization at multiple levels in the testing of the processor, coupled with highly specific test generation constraint rules, highly focused tests on a micro-architectural feature are implemented while at the same time applying a high degree of random permutation in the way it stresses that…
Matrix multiplier with submatrix sequencing
Granted: August 17, 2021
Patent Number:
11093580
A processor sequences the application of submatrices at a matrix multiplier to reduce the number of input changes at an input register of the matrix multiplier. The matrix multiplier is configured to perform a matrix multiplication for a relatively small matrix. To multiply two larger matrices the GPU decomposes the larger matrices into smaller submatrices and stores the submatrices at input registers of the matrix multiplier in a sequence, thereby calculating each column of a result…
Deliberate conditional poison training for generative models
Granted: August 10, 2021
Patent Number:
11087170
A generator for generating artificial data, and training for the same. Data corresponding to a first label is altered within a reference labeled data set. A discriminator is trained based on the reference labeled data set to create a selectively poisoned discriminator. A generator is trained based on the selectively poisoned discriminator to create a selectively poisoned generator. The selectively poisoned generator is tested for the first label and tested for the second label to…
Data transfer acceleration
Granted: August 10, 2021
Patent Number:
11086809
Data transfer acceleration includes receiving, by a data transfer accelerator in a first node of a plurality of nodes, from a second node of the plurality of nodes, a request for data in a second state, wherein the second node stores an instance of the data in a first state; generating a message including one or more operations to transform the data from the first state to the second state; and sending the message to the second node in response to the request.
System and method for load and store queue allocations at address generation time
Granted: August 10, 2021
Patent Number:
11086628
A system and method for load queue (LDQ) and store queue (STQ) entry allocations at address generation time that maintains age-order of instructions is described. In particular, writing LDQ and STQ entries are delayed until address generation time. This allows the load and store operations to dispatch, and younger operations (which may not be store and load operations) to also dispatch and execute their instructions. The address generation of the load or store operation is held at an…
Method and apparatus of cross shader compilation
Granted: August 3, 2021
Patent Number:
11080927
A method and apparatus provides for compiling a plurality of shaders, each shader having a plurality of computer-readable statements, into a plurality of computer-executable instructions. In one example, the method and apparatus, using a computing device, receives the plurality of shaders used in a process pipeline for performing at least one shading function, determines a shader type of each of the plurality of shaders based on the at least one shading function, and compiles the…
Wait instruction for preventing execution of one or more instructions until a load counter or store counter reaches a specified value
Granted: July 27, 2021
Patent Number:
11074075
Systems, apparatuses, and methods for maintaining separate pending load and store counters are disclosed herein. In one embodiment, a system includes at least one execution unit, a memory subsystem, and a pair of counters for each thread of execution. In one embodiment, the system implements a software based approach for managing dependencies between instructions. In one embodiment, the execution unit(s) maintains counters to support the software-based approach for managing dependencies…
Implementing scalable memory allocation using identifiers that return a succinct pointer representation
Granted: July 27, 2021
Patent Number:
11073995
A method and device generates a slab identifier and a hash function identifier in response to a memory allocation request with a request identifier and allocation size from a memory allocation requestor. The slab identifier indicates a memory region associated with a base data size and the hash function identifier indicates a hash function. The method and device provides a bit string including the slab identifier and the hash function identifier to the memory allocation requestor.
Platform power manager for rack level power and thermal constraints
Granted: July 27, 2021
Patent Number:
11073888
Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or…
Mechanism for distributed-system-aware difference encoding/decoding in graph analytics
Granted: July 20, 2021
Patent Number:
11068458
A portion of a graph dataset is generated for each computing node in a distributed computing system by, for each subject vertex in a graph, recording for the computing node an offset for the subject vertex, where the offset references a first position in an edge array for the computing node, and for each edge of a set of edges coupled with the subject vertex in the graph, calculating an edge value for the edge based on a connected vertex identifier identifying a vertex coupled with the…
Automatic part testing
Granted: July 20, 2021
Patent Number:
11068368
Automatic part testing includes: booting a part under testing into a first operating environment; executing, via the first operating environment, one or more test patterns on the part; performing a comparison between one or more observed characteristics associated with the one or more test patterns and one or more expected characteristics; and modifying one or more operational parameters of a central processing unit of the part based on the comparison.
Fine-grained speed binning in an accelerated processing device
Granted: July 13, 2021
Patent Number:
11061429
A technique for fine-granularity speed binning for a processing device is provided. The processing device includes a plurality of clock domains, each of which may be clocked with independent clock signals. The clock frequency at which a particular clock domain may operate is determined based on the longest propagation delay between clocked elements in that particular clock domain. The processing device includes measurement circuits for each clock domain that measure such propagation…
Setting durations for which data is stored in a non-volatile memory based on data types
Granted: July 13, 2021
Patent Number:
11061583
An electronic device includes a non-volatile memory and a controller. The controller receives data to be written to the non-volatile memory and determines a type of the data. Based on the type of the data, the controller selects a given duration of the data from among multiple durations of the data in the non-volatile memory. The controller sets values of one or more parameters for writing the data to the non-volatile memory based on the given duration. The controller writes the data to…
