Method and apparatus for power reduction for data movement
Granted: June 8, 2021
Patent Number:
11030135
A method of and device for transferring data is provided. The method includes determining a difference between a data segment that was transferred last relative to each of one or more data segments available to be transferred next. In some embodiments, for so long as no data segment available to be sent has been waiting too long, the data segment chosen to be sent next is the data segment having the smallest difference relative to the data segment transferred last. The chosen data…
Protecting host memory from access by untrusted accelerators
Granted: June 8, 2021
Patent Number:
11030117
A host processor receives an address translation request from an accelerator, which may be trusted or un-trusted. The address translation request includes a virtual address in a virtual address space that is shared by the host processor and the accelerator. The host processor encrypts a physical address in a host memory indicated by the virtual address in response to the accelerator being permitted to access the physical address. The host processor then provides the encrypted physical…
Virtual space memory bandwidth reduction
Granted: June 8, 2021
Patent Number:
11030095
A processing system includes a central processing unit (CPU) and a graphics processing unit (GPU) that has a plurality of compute units. The GPU receives an image from the CPU and determines a total result area in a virtual-matrix-multiplication space of a virtual matrix-multiplication output matrix based on convolutional parameters associated with the image in an image space. The GPU partitions the total result area of the virtual matrix-multiplication output matrix into a plurality of…
Dedicated interface for coupling flash memory and dynamic random access memory
Granted: June 8, 2021
Patent Number:
11029852
The present application describes embodiments of an interface for coupling flash memory and dynamic random access memory (DRAM) in a processing system. Some embodiments include a dedicated interface between a flash memory and DRAM. The dedicated interface is to provide access to the flash memory in response to instructions received over a DRAM interface between the DRAM and a processing device. Some embodiments of a method include accessing a flash memory via a dedicated interface…
Methods and apparatus for decoding video using re-ordered motion vector buffer
Granted: June 1, 2021
Patent Number:
11025934
A host processor, such as a central processing unit (CPU), programmed to execute a software driver that causes the host processor to generate a motion compensation command for a plurality of cores of a massively parallel processor, such as a graphics processing unit (GPU), to provide motion compensation for encoded video. The motion compensation command for the plurality of cores of the massively parallel processor contains executable instructions for processing a plurality of motion…
Instructions for performing multi-line memory accesses
Granted: June 1, 2021
Patent Number:
11023410
A system is described that performs memory access operations. The system includes a processor in a first node, a memory in a second node, a communication interconnect coupled to the processor and the memory, and an interconnect controller in the first node coupled between the processor and the communication interconnect. Upon executing a multi-line memory access instruction, the processor prepares a memory access operation for accessing, in the memory, a block of data including at least…
Method and apparatus for asynchronous scheduling
Granted: June 1, 2021
Patent Number:
11023242
A method and apparatus of asynchronous scheduling in a graphics device includes sending one or more instructions from an instruction scheduler to one or more instruction first-in/first-out (FIFO) devices. An instruction in the one or more FIFO devices is selected for execution by a single-instruction/multiple-data (SIMD) pipeline unit. It is determined whether all operands for the selected instruction are available for execution of the instruction, and if all the operands are available,…
Systems and methods for selectively bypassing address-generation hardware in processor instruction pipelines
Granted: June 1, 2021
Patent Number:
11023241
Systems and methods selectively bypass address-generation hardware in processor instruction pipelines. In an embodiment, a processor includes an address-generation stage and an address-generation-bypass-determination unit (ABDU). The ABDU receives a load/store instruction. If an effective address for the load/store instruction is not known at the ABDU, the ABDU routes the load/store instruction via the address-generation stage of the processor. If, however, the effective address of the…
Implementing a micro-operation cache with compaction
Granted: May 25, 2021
Patent Number:
11016763
Systems, apparatuses, and methods for compacting multiple groups of micro-operations into individual cache lines of a micro-operation cache are disclosed. A processor includes at least a decode unit and a micro-operation cache. When a new group of micro-operations is decoded and ready to be written to the micro-operation cache, the micro-operation cache determines which set is targeted by the new group of micro-operations. If there is a way in this set that can store the new group…
Multi-chip package with offset 3D structure
Granted: May 25, 2021
Patent Number:
11018125
Various semiconductor chip devices and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that has a reconstituted semiconductor chip package that includes an interposer that has a first side and a second and opposite side and a metallization stack on the first side, a first semiconductor chip on the metallization stack and at least partially encased by a dielectric layer on the metallization stack, and plural semiconductor chips…
Control of performance levels of different types of processors via a user interface
Granted: May 25, 2021
Patent Number:
11016555
An apparatus and a method for controlling power consumption associated with a computing device having first and second processors configured to perform different types of operations includes providing a user interface that allows, during normal operation of the computing device, at least one of: (i) a user selection of desired performance levels of the first and second processors relative to one another, such that higher desired performance levels of one processor correspond to lower…
Multiple-die integrated circuit with integrated voltage regulator
Granted: May 18, 2021
Patent Number:
11011495
A data processor is implemented as an integrated circuit. The data processor includes a processor die. The processor die is connected to an integrated voltage regulator die using die-to-die bonding. The integrated voltage regulator die provides a regulated voltage to the processor die, and the processor die operates in response to the regulated voltage.
Integrated circuit package with integrated voltage regulator
Granted: May 18, 2021
Patent Number:
11011466
Various semiconductor chip devices and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer (RDL) structure having a first plurality of conductor traces, a first molding layer on the first RDL structure, plural conductive pillars in the first molding layer, each of the conductive pillars including a first end and a second end, a second RDL structure on the first molding layer, the second RDL structure having a second…
Reduced bandwidth tessellation factors
Granted: May 18, 2021
Patent Number:
11010862
A graphics pipeline reduces the number of tessellation factors written to and read from a graphics memory. A hull shader stage of the graphics pipeline detects whether at least a threshold percentage of the tessellation factors for a thread group of patches are the same and, in some embodiments, whether at least the threshold percentage of the tessellation factors for a thread group of patches have a same value that either indicates that the plurality of patches are to be culled or that…
Semiconductor chip with stacked conductor lines and air gaps
Granted: May 11, 2021
Patent Number:
11004791
Various semiconductor chip metallization layers and methods of manufacturing the same are disclosed. In aspect, a semiconductor chip is provided that includes a substrate, plural metallization layers on the substrate, a first conductor line in one of the metallization layers and a second conductor line in the one of the metallization layers in spaced apart relation to the first conductor line, each of the first conductor line and the second conductor line has a first line portion and a…
Combined world-space pipeline shader stages
Granted: May 11, 2021
Patent Number:
11004258
Improvements to graphics processing pipelines are disclosed. More specifically, the vertex shader stage, which performs vertex transformations, and the hull or geometry shader stages, are combined. If tessellation is disabled and geometry shading is enabled, then the graphics processing pipeline includes a combined vertex and graphics shader stage. If tessellation is enabled, then the graphics processing pipeline includes a combined vertex and hull shader stage. If tessellation and…
Automatic configuration of knobs to optimize performance of a graphics pipeline
Granted: May 11, 2021
Patent Number:
11004251
A knob has a plurality of settings that configure a graphics pipeline. A first setting is associated with a first state of the graphics pipeline. The first setting is associated with the first state based on a measure of performance of the graphics pipeline while configured according to the first setting. The graphics pipeline is configured according to the first setting in response to the first state of the graphics pipeline matching a current state of the graphics pipeline. The…
Networked input/output memory management unit
Granted: May 11, 2021
Patent Number:
11003588
A networked input/output memory management unit (IOMMU) includes a plurality of IOMMUs. The networked IOMMU receives a memory access request that includes a domain physical address generated by a first address translation layer. The networked IOMMU selectively translates the domain physical address into a physical address in a system memory using one of the plurality of IOMMUs that is selected based on a type of a device that generated the memory access request. In some cases, the…
Low latency FIFO with auto sync
Granted: April 27, 2021
Patent Number:
10990120
A method operates a first-in-first-out (FIFO) buffer with a first clock, and operates one of a read pointer or a write pointer of the FIFO buffer with the first clock while operating the other one of the read pointer or write pointer with a second clock. One of a serializer fed from the FIFO buffer output, or a de-serializer feeding the FIFO buffer input, is operated with the second clock. Timing pulses indicate that the pointer operating with the second clock has reached a predetermined…
Address-based filtering for load/store speculation
Granted: April 27, 2021
Patent Number:
10990393
Address-based filtering for load/store speculation includes maintaining a filtering table including table entries associated with ranges of addresses; in response to receiving an ordering check triggering transaction, querying the filtering table using a target address of the ordering check triggering transaction to determine if an instruction dependent upon the ordering check triggering transaction has previously been generated a physical address; and in response to determining that the…
