Address-based filtering for load/store speculation
Granted: April 27, 2021
Patent Number:
10990393
Address-based filtering for load/store speculation includes maintaining a filtering table including table entries associated with ranges of addresses; in response to receiving an ordering check triggering transaction, querying the filtering table using a target address of the ordering check triggering transaction to determine if an instruction dependent upon the ordering check triggering transaction has previously been generated a physical address; and in response to determining that the…
Low latency FIFO with auto sync
Granted: April 27, 2021
Patent Number:
10990120
A method operates a first-in-first-out (FIFO) buffer with a first clock, and operates one of a read pointer or a write pointer of the FIFO buffer with the first clock while operating the other one of the read pointer or write pointer with a second clock. One of a serializer fed from the FIFO buffer output, or a de-serializer feeding the FIFO buffer input, is operated with the second clock. Timing pulses indicate that the pointer operating with the second clock has reached a predetermined…
Interposer-based damping resistor
Granted: April 20, 2021
Patent Number:
10985097
Various resistor circuits and methods of making and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a resistor onboard an interposer. The resistor is adapted to dampen a capacitive network. The capacitive network has at least one capacitor positioned external to the interposer.
Interconnect architecture for three-dimensional processing systems
Granted: April 20, 2021
Patent Number:
10984838
A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with the first layer. Each of the partitions is associated with a subset of the processor cores that have overlapping footprints with the partitions. The processing system also includes first…
Flexible dictionary sharing for compressed caches
Granted: April 20, 2021
Patent Number:
10983915
Systems, apparatuses, and methods for implementing flexible dictionary sharing techniques for caches are disclosed. A set-associative cache includes a dictionary for each data array set. When a cache line is to be allocated in the cache, a cache controller determines to which set a base index of the cache line address maps. Then, a selector unit determines which dictionary of a group of dictionaries stored by those sets neighboring this set would achieve the most compression for the…
Methods and apparatus for optical blur modeling for improved video encoding
Granted: April 13, 2021
Patent Number:
10979704
Methods and apparatus of generating a refined reference frame for inter-frame encoding by applying blur parameters to allow encoding of image frames having blurred regions are presented herein. The methods and apparatus may identify a blurred region of an image frame by comparing the image frame with a reference frame, generate a refined reference frame by applying the blur parameter indicative of the blurred region to the reference frame, determine whether to use one of the reference…
Stream processor with decoupled crossbar for cross lane operations
Granted: April 6, 2021
Patent Number:
10970081
Systems, apparatuses, and methods for implementing a decoupled crossbar for a stream processor are disclosed. In one embodiment, a system includes at least a multi-lane execution pipeline, a vector register file, and a crossbar. The system is configured to determine if a given instruction in an instruction stream requires a permutation on data operands retrieved from the vector register file. The system conveys the data operands to the multi-lane execution pipeline on a first path which…
Stereoscopic interleaved compression
Granted: April 6, 2021
Patent Number:
10972752
Systems, apparatuses, and methods for implementing stereoscopic interleaved compression techniques are disclosed. A system includes a transmitter sending a video stream over a wireless link to a receiver. For each pair of frames, the transmitter encodes a left-half of a first frame of the pair with an amount of compression less than a first threshold and encodes a right-half of the first frame with an amount of compression greater than a second threshold. For a second frame of the pair,…
Method and system for opportunistic load balancing in neural networks using metadata
Granted: April 6, 2021
Patent Number:
10970120
Methods and systems for opportunistic load balancing in deep neural networks (DNNs) using metadata. Representative computational costs are captured, obtained or determined for a given architectural, functional or computational aspect of a DNN system. The representative computational costs are implemented as metadata for the given architectural, functional or computational aspect of the DNN system. In an implementation, the computed computational cost is implemented as the metadata. A…
Shareable FPGA compute engine
Granted: April 6, 2021
Patent Number:
10970118
Systems, apparatuses, and methods for sharing an field programmable gate array compute engine are disclosed. A system includes one or more processors and one or more FPGAs. The system receives a request, generated by a first user process, to allocate a portion of processing resources on a first FPGA. The system maps the portion of processing resources of the first FPGA into an address space of the first user process. The system prevents other user processes from accessing the portion of…
Using age matrices for managing entries in sub-queues of a queue
Granted: March 30, 2021
Patent Number:
10963402
An electronic device includes a queue with multiple sub-queues arranged in a logical hierarchy from a lowest sub-queue to a highest sub-queue, each sub-queue including a separate subset of a set of entries of the queue, and a separate age matrix for each sub-queue. The electronic device also includes a controller that stores items in entries in the lowest sub-queue until the lowest sub-queue is full and then stores items in successively next higher sub-queues in the hierarchy. The…
Network interface controller-based scheduling of processing tasks in a distributed computing system
Granted: March 30, 2021
Patent Number:
10963309
Techniques for scheduling processing tasks in a device having multiple computing elements are disclosed. A network interface controller of the device receives processing tasks, for execution on the computing elements, from a network that is external to the device. The network interface controller schedules the tasks for execution on the computing devices based on policy data available to the network interface controller. A scheduler within the network interface controller, which can be…
Hardware accelerated dynamic work creation on a graphics processing unit
Granted: March 30, 2021
Patent Number:
10963299
A processor core is configured to execute a parent task that is described by a data structure stored in a memory. A coprocessor is configured to dispatch a child task to the at least one processor core in response to the coprocessor receiving a request from the parent task concurrently with the parent task executing on the at least one processor core. In some cases, the parent task registers the child task in a task pool and the child task is a future task that is configured to monitor a…
Hypervisor post-write notification of control and debug register updates
Granted: March 30, 2021
Patent Number:
10963280
Systems, apparatuses, and methods for implementing hypervisor post-write notification of processor state register modifications. A write to a state register of the processor may be detected during guest execution. In response to detecting the write to the state register, the processor may trigger microcode to perform the write and copy the new value of the register to a memory location prior to exiting the guest. The hypervisor may be notified of the update to the state register after it…
Saving power in the command processor using queue based watermarks
Granted: March 23, 2021
Patent Number:
10955901
Systems, apparatuses, and methods for dynamically adjusting the power consumption of prefetch engines are disclosed. In one embodiment, a processor includes one or more prefetch engines, a draw completion engine, and a queue in between the one or more prefetch engines and the draw completion engine. If the number of packets stored in the queue is greater than a high watermark, then the processor reduces the power state of the prefetch engine(s). By decreasing the power state of the…
Back side metallization
Granted: March 23, 2021
Patent Number:
10957669
An integrated circuit device wafer includes a silicon wafer substrate and a back side metallization structure. The back side metallization structure includes a first adhesion layer on the back side of the substrate, a first metal later over the first adhesion layer, a second metal layer over the first metal layer, and a second adhesion layer over the second metal layer. The first includes at least one of: silicon nitride and silicon dioxide. The first metal layer includes titanium. The…
Retaining cache entries of a processor core during a powered-down state
Granted: March 23, 2021
Patent Number:
10956332
A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first cache are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of…
Processor support for hardware transactional memory
Granted: March 23, 2021
Patent Number:
10956163
A processing core of a plurality of processing cores is configured to execute a speculative region of code a single atomic memory transaction with respect one or more others of the plurality of processing cores. In response to determining an abort condition for issued one of the plurality of program instructions and in response to determining that the issued program instruction is not part of a mispredicted execution path, the processing core is configured to abort an attempt to execute…
Taint protection during speculative execution
Granted: March 23, 2021
Patent Number:
10956157
A subset of a set of architectural registers in a processing system is marked (or “tainted”) to indicate that speculative use of data in the subset of the architectural registers is constrained based on a taint handling policy. One or more speculation features supported by the processing system are disabled for the instruction so that the one or more speculation features cannot be used on data in the subset. In some cases, values of bits associated with the subset of architectural…
Memory system with region-specific memory access scheduling
Granted: March 23, 2021
Patent Number:
10956044
An integrated circuit device includes a memory controller coupleable to a memory. The memory controller to schedule memory accesses to regions of the memory based on memory timing parameters specific to the regions. A method includes receiving a memory access request at a memory device. The method further includes accessing, from a timing data store of the memory device, data representing a memory timing parameter specific to a region of the memory cell circuitry targeted by the memory…
